Improved double noise coupling ΔΣ analog-to-digital converter
In Jung et al. (Electron Lett 48(10):557–558, 1 ), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is prese...
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| Veröffentlicht in: | Analog integrated circuits and signal processing 2017-06, Vol.91 (3), p.399-402 |
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| creator | Jung, Youngho Temes, Gabor C. |
| description | In Jung et al. (Electron Lett 48(10):557–558,
1
), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference,
2
). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly. |
| doi_str_mv | 10.1007/s10470-017-0955-x |
| format | Article |
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1
), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference,
2
). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly.</description><identifier>ISSN: 0925-1030</identifier><identifier>EISSN: 1573-1979</identifier><identifier>DOI: 10.1007/s10470-017-0955-x</identifier><language>eng</language><publisher>New York: Springer US</publisher><subject>Analog to digital conversion ; Analog to digital converters ; Broadband ; Circuits ; Circuits and Systems ; Coupling ; Electrical Engineering ; Electronics industry ; Engineering ; High speed ; Noise ; Power consumption ; Sampling techniques ; Signal,Image and Speech Processing</subject><ispartof>Analog integrated circuits and signal processing, 2017-06, Vol.91 (3), p.399-402</ispartof><rights>Springer Science+Business Media New York 2017</rights><rights>Copyright Springer Science & Business Media 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c183x-936426da0a324ee53a0073364942e7838915e434e559b5b1f9b68b45cadb548e3</cites><orcidid>0000-0002-8754-3301</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s10470-017-0955-x$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s10470-017-0955-x$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>315,781,785,27929,27930,41493,42562,51324</link.rule.ids></links><search><creatorcontrib>Jung, Youngho</creatorcontrib><creatorcontrib>Temes, Gabor C.</creatorcontrib><title>Improved double noise coupling ΔΣ analog-to-digital converter</title><title>Analog integrated circuits and signal processing</title><addtitle>Analog Integr Circ Sig Process</addtitle><description>In Jung et al. (Electron Lett 48(10):557–558,
1
), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference,
2
). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly.</description><subject>Analog to digital conversion</subject><subject>Analog to digital converters</subject><subject>Broadband</subject><subject>Circuits</subject><subject>Circuits and Systems</subject><subject>Coupling</subject><subject>Electrical Engineering</subject><subject>Electronics industry</subject><subject>Engineering</subject><subject>High speed</subject><subject>Noise</subject><subject>Power consumption</subject><subject>Sampling techniques</subject><subject>Signal,Image and Speech Processing</subject><issn>0925-1030</issn><issn>1573-1979</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><recordid>eNp1kE1OwzAUhC0EEqVwAHaRWBueYzuxVwhV_FSqxAbWlpO8RqnSuNhJFe7BDbhPz4SrsGDD6knzZkajj5BrBrcMIL8LDEQOFFhOQUtJxxMyYzLnlOlcn5IZ6FRSBhzOyUUIGwBIcwEzcr_c7rzbY5VUbihaTDrXBExKN-zapquTw9fhO7GdbV1Ne0erpm5628Z_t0ffo78kZ2vbBrz6vXPy_vT4tnihq9fn5eJhRUum-Eg1z0SaVRYsTwWi5DaO5lHUIsVccaWZRMEFSqkLWbC1LjJVCFnaqpBCIZ-Tm6k3rv0YMPRm4wYfdwXDlE65Ulpk0cUmV-ldCB7XZuebrfWfhoE5cjITJxM5mSMnM8ZMOmVC9HY1-j_N_4Z-AIeZa3A</recordid><startdate>20170601</startdate><enddate>20170601</enddate><creator>Jung, Youngho</creator><creator>Temes, Gabor C.</creator><general>Springer US</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TG</scope><scope>8FD</scope><scope>KL.</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-8754-3301</orcidid></search><sort><creationdate>20170601</creationdate><title>Improved double noise coupling ΔΣ analog-to-digital converter</title><author>Jung, Youngho ; Temes, Gabor C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c183x-936426da0a324ee53a0073364942e7838915e434e559b5b1f9b68b45cadb548e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Analog to digital conversion</topic><topic>Analog to digital converters</topic><topic>Broadband</topic><topic>Circuits</topic><topic>Circuits and Systems</topic><topic>Coupling</topic><topic>Electrical Engineering</topic><topic>Electronics industry</topic><topic>Engineering</topic><topic>High speed</topic><topic>Noise</topic><topic>Power consumption</topic><topic>Sampling techniques</topic><topic>Signal,Image and Speech Processing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jung, Youngho</creatorcontrib><creatorcontrib>Temes, Gabor C.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Meteorological & Geoastrophysical Abstracts</collection><collection>Technology Research Database</collection><collection>Meteorological & Geoastrophysical Abstracts - Academic</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Analog integrated circuits and signal processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Jung, Youngho</au><au>Temes, Gabor C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Improved double noise coupling ΔΣ analog-to-digital converter</atitle><jtitle>Analog integrated circuits and signal processing</jtitle><stitle>Analog Integr Circ Sig Process</stitle><date>2017-06-01</date><risdate>2017</risdate><volume>91</volume><issue>3</issue><spage>399</spage><epage>402</epage><pages>399-402</pages><issn>0925-1030</issn><eissn>1573-1979</eissn><abstract>In Jung et al. (Electron Lett 48(10):557–558,
1
), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference,
2
). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly.</abstract><cop>New York</cop><pub>Springer US</pub><doi>10.1007/s10470-017-0955-x</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-8754-3301</orcidid></addata></record> |
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| subjects | Analog to digital conversion Analog to digital converters Broadband Circuits Circuits and Systems Coupling Electrical Engineering Electronics industry Engineering High speed Noise Power consumption Sampling techniques Signal,Image and Speech Processing |
| title | Improved double noise coupling ΔΣ analog-to-digital converter |
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