Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems

In this work we investigate a new background calibration technique to compensate sampling phase errors in time-interleaved analog-to-digital-converters (TI-ADCs). Timing mismatches in TI-ADC degrade significantly the performance of ultra-high-speed digital transceivers. Unlike previous proposals, th...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2017-05, Vol.64 (5), p.1019-1030
Hauptverfasser:	Reyes, Benjamin T., Sanchez, Raul M., Pola, Ariel L., Hueda, Mario R.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithm design and analysis Algorithms Analog to digital conversion Analog to digital converters Calibration Communication systems Communications systems Cross correlation Digital signal processing Errors Field programmable gate arrays FPGA fractional-spaced equalizer High speed Low speed Phase control Receivers Sampling Signal processing Signal processing algorithms Signal to noise ratio State machines TI-ADC Time lag time-error calibration Transceivers
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