DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers
In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase no...
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Veröffentlicht in: | IEEE journal of solid-state circuits 2017-04, Vol.52 (4), p.1134-1143 |
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creator | Zuow-Zun Chen Yen-Cheng Kuan Yilei Li Boyu Hu Chien-Heng Wong Chang, Mau-Chung Frank |
description | In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz. |
doi_str_mv | 10.1109/JSSC.2017.2647925 |
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The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. 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The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz.</description><subject>Background noise</subject><subject>Baseband</subject><subject>CMOS</subject><subject>Digital phase-locked loop (DPLL)</subject><subject>Digital technology</subject><subject>frequency synthesizer</subject><subject>Microwave communications</subject><subject>Noise</subject><subject>Noise reduction</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><subject>phase noise cancellation</subject><subject>Quantization (signal)</subject><subject>radio receiver</subject><subject>Receivers</subject><subject>ring oscillator (RO)</subject><subject>sub-sampling time-to-digital converter (TDC)</subject><subject>Test methods</subject><subject>Transfer functions</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1LAzEQhoMoWKs_QLwEPG_N5HuPun5TbG0VvIVsmtWUuqvJruC_d5cWLzPM8Lwz8CB0CmQCQPKLx-WymFACakIlVzkVe2gEQugMFHvbRyNCQGc5JeQQHaW07kfONYzQ7Ho-neKqiXj-YZPHT03oa2Fr5zcb24amxqHGi1C_41lyYdg1Mbvq0RV-7uwq2raLHi-88-HHx3SMDiq7Sf5k18fo9fbmpbjPprO7h-JymjmaszbLufM5rcjKQcmd5hIYcF1xUjonBJGcKaLBWisl5KByqcqeJ4o48KUgFRuj8-3dr9h8dz61Zt10se5fGtCaMSEU5T0FW8rFJqXoK_MVw6eNvwaIGbyZwZsZvJmdtz5zts0E7_0_r7SkwCX7A1qyZ5k</recordid><startdate>20170401</startdate><enddate>20170401</enddate><creator>Zuow-Zun Chen</creator><creator>Yen-Cheng Kuan</creator><creator>Yilei Li</creator><creator>Boyu Hu</creator><creator>Chien-Heng Wong</creator><creator>Chang, Mau-Chung Frank</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2017.2647925</doi><tpages>10</tpages><orcidid>https://orcid.org/0000-0003-1948-305X</orcidid></addata></record> |
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subjects | Background noise Baseband CMOS Digital phase-locked loop (DPLL) Digital technology frequency synthesizer Microwave communications Noise Noise reduction Phase locked loops Phase noise phase noise cancellation Quantization (signal) radio receiver Receivers ring oscillator (RO) sub-sampling time-to-digital converter (TDC) Test methods Transfer functions |
title | DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers |
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