Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach
We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows...
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Veröffentlicht in: | IEEE transactions on electron devices 2017-03, Vol.64 (3), p.1069-1075 |
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creator | Lyu, Rong-Jhe Shie, Bo-Shiuan Lin, Horng-Chih Li, Pei-Wen Huang, Tiao-Yuan |
description | We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9 ×10 7 and 4.2 × 10 7 , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics. |
doi_str_mv | 10.1109/TED.2016.2646221 |
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The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9 ×10 7 and 4.2 × 10 7 , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2016.2646221</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bridges ; Fabrication ; Film profile engineering (FPE) ; II-VI semiconductor materials ; Logic gates ; metal oxide (MO) ; Metal oxides ; short channel effects (SCEs) ; Thin film transistors ; thin-film transistors (TFTs) ; Tin ; Zinc oxide ; ZnO</subject><ispartof>IEEE transactions on electron devices, 2017-03, Vol.64 (3), p.1069-1075</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-69922b0b644d9cc072629e588e96d16e65608a7f388c5f088da62adc777265773</citedby><cites>FETCH-LOGICAL-c291t-69922b0b644d9cc072629e588e96d16e65608a7f388c5f088da62adc777265773</cites><orcidid>0000-0003-0662-9435</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7808990$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7808990$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lyu, Rong-Jhe</creatorcontrib><creatorcontrib>Shie, Bo-Shiuan</creatorcontrib><creatorcontrib>Lin, Horng-Chih</creatorcontrib><creatorcontrib>Li, Pei-Wen</creatorcontrib><creatorcontrib>Huang, Tiao-Yuan</creatorcontrib><title>Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9 ×10 7 and 4.2 × 10 7 , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.</description><subject>Bridges</subject><subject>Fabrication</subject><subject>Film profile engineering (FPE)</subject><subject>II-VI semiconductor materials</subject><subject>Logic gates</subject><subject>metal oxide (MO)</subject><subject>Metal oxides</subject><subject>short channel effects (SCEs)</subject><subject>Thin film transistors</subject><subject>thin-film transistors (TFTs)</subject><subject>Tin</subject><subject>Zinc oxide</subject><subject>ZnO</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kF1LwzAUhoMoOKf3gjcBrzOTtM3H5dg6FSYTrNclS9Mto0u3pMX5703Z8OrwwnPOe3gAeCR4QgiWL0U-n1BM2ISylFFKrsCIZBlHMsZrMMKYCCQTkdyCuxB2MbI0pSPQzNsfF7RqrNvAD9OpBq1OtjKw2FqHFrbZw8IrF2zoWh9g18Kvfo0yDN0eWgeVg_np2NtgOwMHGn36traNgbnbWGeMH-5ODwffKr29Bze1aoJ5uMwx-F7kxewNLVev77PpEmkqSYeYlJSu8Tp-WEmtMaeMSpMJYSSrCDMsY1goXidC6KzGQlSKUVVpziOZcZ6MwfP5bqw99iZ05a7tvYuVJRE8iX6YTCOFz5T2bQje1OXB273yvyXB5eC0jE7LwWl5cRpXns4r1hjzj3OBhZQ4-QOu73Em</recordid><startdate>20170301</startdate><enddate>20170301</enddate><creator>Lyu, Rong-Jhe</creator><creator>Shie, Bo-Shiuan</creator><creator>Lin, Horng-Chih</creator><creator>Li, Pei-Wen</creator><creator>Huang, Tiao-Yuan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-0662-9435</orcidid></search><sort><creationdate>20170301</creationdate><title>Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach</title><author>Lyu, Rong-Jhe ; Shie, Bo-Shiuan ; Lin, Horng-Chih ; Li, Pei-Wen ; Huang, Tiao-Yuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-69922b0b644d9cc072629e588e96d16e65608a7f388c5f088da62adc777265773</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Bridges</topic><topic>Fabrication</topic><topic>Film profile engineering (FPE)</topic><topic>II-VI semiconductor materials</topic><topic>Logic gates</topic><topic>metal oxide (MO)</topic><topic>Metal oxides</topic><topic>short channel effects (SCEs)</topic><topic>Thin film transistors</topic><topic>thin-film transistors (TFTs)</topic><topic>Tin</topic><topic>Zinc oxide</topic><topic>ZnO</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lyu, Rong-Jhe</creatorcontrib><creatorcontrib>Shie, Bo-Shiuan</creatorcontrib><creatorcontrib>Lin, Horng-Chih</creatorcontrib><creatorcontrib>Li, Pei-Wen</creatorcontrib><creatorcontrib>Huang, Tiao-Yuan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lyu, Rong-Jhe</au><au>Shie, Bo-Shiuan</au><au>Lin, Horng-Chih</au><au>Li, Pei-Wen</au><au>Huang, Tiao-Yuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2017-03-01</date><risdate>2017</risdate><volume>64</volume><issue>3</issue><spage>1069</spage><epage>1075</epage><pages>1069-1075</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9 ×10 7 and 4.2 × 10 7 , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2016.2646221</doi><tpages>7</tpages><orcidid>https://orcid.org/0000-0003-0662-9435</orcidid></addata></record> |
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subjects | Bridges Fabrication Film profile engineering (FPE) II-VI semiconductor materials Logic gates metal oxide (MO) Metal oxides short channel effects (SCEs) Thin film transistors thin-film transistors (TFTs) Tin Zinc oxide ZnO |
title | Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach |
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