A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phaselocked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization er...

Ausführliche Beschreibung