Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs

In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. To solve this issue, an iterative approach called incremental step pulse progr...

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Veröffentlicht in:	IEEE journal on selected areas in communications 2016-09, Vol.34 (9), p.2325-2335
Hauptverfasser:	Asadi, Meysam, Haratsch, Erich F., Kavcic, Aleksandar, Santhanam, Narayana Prasad
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer architecture ICI interference ISPP latency lifetime Logic gates Microprocessors MLC NAND flash Programming renewal process Threshold voltage Transistors
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