Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs
In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. To solve this issue, an iterative approach called incremental step pulse progr...
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| Veröffentlicht in: | IEEE journal on selected areas in communications 2016-09, Vol.34 (9), p.2325-2335 |
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| container_title | IEEE journal on selected areas in communications |
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| creator | Asadi, Meysam Haratsch, Erich F. Kavcic, Aleksandar Santhanam, Narayana Prasad |
| description | In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. To solve this issue, an iterative approach called incremental step pulse programming (ISPP) is used to concurrently program lots of cells in small steps. In this paper, we are mostly concerned with deriving a mathematical model for iterative programming using the framework of renewal theory. We obtain a closed-form approximation for the probability distribution of the number of steps required in the ISPP process. We also bound the maximal error between the true distribution and our approximation. Moreover, the results obtained help to accurately analyze the effect of inter-cell interference in this type of memory. Finally, we devise an adaptive step size approach for write process to strike a balance between latency and lifetime under fixed bit error rate constraints or information rate constraints. |
| doi_str_mv | 10.1109/JSAC.2016.2604058 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_1831025700</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7556371</ieee_id><sourcerecordid>4224054681</sourcerecordid><originalsourceid>FETCH-LOGICAL-c245t-fd6d3490c2928484e9fafcb903cc57710380864846b0dd3b0211c01cdfffe8f3</originalsourceid><addsrcrecordid>eNo9kEFPwkAQhTdGExH9AcZLE8_Fmd1uu_VgQlAUg5FI75uyOysl0OIuxPDvLSnxNIf3vTfJx9gtwgAR8of3-XA04IDpgKeQgFRnrIdSqhgA1DnrQSZErDJML9lVCCsATBLFe-xpvC7DMvqgTeMrCo_RZD6bRV9U02-5joolNf4QlbWNOu6ZQvVdR4UvLTXOhWt24cp1oJvT7bNi_FKM3uLp5-tkNJzGhidyFzubWpHkYHjOVaISyl3pzCIHYYzMMgShQKVtkC7AWrEAjmgAjXXOkXKiz-672a1vfvYUdnrV7H3dftSoBAKXGUBLYUcZ34TgyemtrzalP2gEfbSkj5b00ZI-WWo7d12nIqJ_PpMyFRmKP8SLYRo</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1831025700</pqid></control><display><type>article</type><title>Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs</title><source>IEEE Electronic Library (IEL)</source><creator>Asadi, Meysam ; Haratsch, Erich F. ; Kavcic, Aleksandar ; Santhanam, Narayana Prasad</creator><creatorcontrib>Asadi, Meysam ; Haratsch, Erich F. ; Kavcic, Aleksandar ; Santhanam, Narayana Prasad</creatorcontrib><description>In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. To solve this issue, an iterative approach called incremental step pulse programming (ISPP) is used to concurrently program lots of cells in small steps. In this paper, we are mostly concerned with deriving a mathematical model for iterative programming using the framework of renewal theory. We obtain a closed-form approximation for the probability distribution of the number of steps required in the ISPP process. We also bound the maximal error between the true distribution and our approximation. Moreover, the results obtained help to accurately analyze the effect of inter-cell interference in this type of memory. Finally, we devise an adaptive step size approach for write process to strike a balance between latency and lifetime under fixed bit error rate constraints or information rate constraints.</description><identifier>ISSN: 0733-8716</identifier><identifier>EISSN: 1558-0008</identifier><identifier>DOI: 10.1109/JSAC.2016.2604058</identifier><identifier>CODEN: ISACEM</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Computer architecture ; ICI interference ; ISPP ; latency ; lifetime ; Logic gates ; Microprocessors ; MLC NAND flash ; Programming ; renewal process ; Threshold voltage ; Transistors</subject><ispartof>IEEE journal on selected areas in communications, 2016-09, Vol.34 (9), p.2325-2335</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c245t-fd6d3490c2928484e9fafcb903cc57710380864846b0dd3b0211c01cdfffe8f3</cites><orcidid>0000-0002-7492-7031</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7556371$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7556371$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Asadi, Meysam</creatorcontrib><creatorcontrib>Haratsch, Erich F.</creatorcontrib><creatorcontrib>Kavcic, Aleksandar</creatorcontrib><creatorcontrib>Santhanam, Narayana Prasad</creatorcontrib><title>Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs</title><title>IEEE journal on selected areas in communications</title><addtitle>J-SAC</addtitle><description>In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. To solve this issue, an iterative approach called incremental step pulse programming (ISPP) is used to concurrently program lots of cells in small steps. In this paper, we are mostly concerned with deriving a mathematical model for iterative programming using the framework of renewal theory. We obtain a closed-form approximation for the probability distribution of the number of steps required in the ISPP process. We also bound the maximal error between the true distribution and our approximation. Moreover, the results obtained help to accurately analyze the effect of inter-cell interference in this type of memory. Finally, we devise an adaptive step size approach for write process to strike a balance between latency and lifetime under fixed bit error rate constraints or information rate constraints.</description><subject>Computer architecture</subject><subject>ICI interference</subject><subject>ISPP</subject><subject>latency</subject><subject>lifetime</subject><subject>Logic gates</subject><subject>Microprocessors</subject><subject>MLC NAND flash</subject><subject>Programming</subject><subject>renewal process</subject><subject>Threshold voltage</subject><subject>Transistors</subject><issn>0733-8716</issn><issn>1558-0008</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEFPwkAQhTdGExH9AcZLE8_Fmd1uu_VgQlAUg5FI75uyOysl0OIuxPDvLSnxNIf3vTfJx9gtwgAR8of3-XA04IDpgKeQgFRnrIdSqhgA1DnrQSZErDJML9lVCCsATBLFe-xpvC7DMvqgTeMrCo_RZD6bRV9U02-5joolNf4QlbWNOu6ZQvVdR4UvLTXOhWt24cp1oJvT7bNi_FKM3uLp5-tkNJzGhidyFzubWpHkYHjOVaISyl3pzCIHYYzMMgShQKVtkC7AWrEAjmgAjXXOkXKiz-672a1vfvYUdnrV7H3dftSoBAKXGUBLYUcZ34TgyemtrzalP2gEfbSkj5b00ZI-WWo7d12nIqJ_PpMyFRmKP8SLYRo</recordid><startdate>20160901</startdate><enddate>20160901</enddate><creator>Asadi, Meysam</creator><creator>Haratsch, Erich F.</creator><creator>Kavcic, Aleksandar</creator><creator>Santhanam, Narayana Prasad</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-7492-7031</orcidid></search><sort><creationdate>20160901</creationdate><title>Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs</title><author>Asadi, Meysam ; Haratsch, Erich F. ; Kavcic, Aleksandar ; Santhanam, Narayana Prasad</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c245t-fd6d3490c2928484e9fafcb903cc57710380864846b0dd3b0211c01cdfffe8f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Computer architecture</topic><topic>ICI interference</topic><topic>ISPP</topic><topic>latency</topic><topic>lifetime</topic><topic>Logic gates</topic><topic>Microprocessors</topic><topic>MLC NAND flash</topic><topic>Programming</topic><topic>renewal process</topic><topic>Threshold voltage</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Asadi, Meysam</creatorcontrib><creatorcontrib>Haratsch, Erich F.</creatorcontrib><creatorcontrib>Kavcic, Aleksandar</creatorcontrib><creatorcontrib>Santhanam, Narayana Prasad</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal on selected areas in communications</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Asadi, Meysam</au><au>Haratsch, Erich F.</au><au>Kavcic, Aleksandar</au><au>Santhanam, Narayana Prasad</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs</atitle><jtitle>IEEE journal on selected areas in communications</jtitle><stitle>J-SAC</stitle><date>2016-09-01</date><risdate>2016</risdate><volume>34</volume><issue>9</issue><spage>2325</spage><epage>2335</epage><pages>2325-2335</pages><issn>0733-8716</issn><eissn>1558-0008</eissn><coden>ISACEM</coden><abstract>In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. To solve this issue, an iterative approach called incremental step pulse programming (ISPP) is used to concurrently program lots of cells in small steps. In this paper, we are mostly concerned with deriving a mathematical model for iterative programming using the framework of renewal theory. We obtain a closed-form approximation for the probability distribution of the number of steps required in the ISPP process. We also bound the maximal error between the true distribution and our approximation. Moreover, the results obtained help to accurately analyze the effect of inter-cell interference in this type of memory. Finally, we devise an adaptive step size approach for write process to strike a balance between latency and lifetime under fixed bit error rate constraints or information rate constraints.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSAC.2016.2604058</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0002-7492-7031</orcidid><oa>free_for_read</oa></addata></record> |
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| subjects | Computer architecture ICI interference ISPP latency lifetime Logic gates Microprocessors MLC NAND flash Programming renewal process Threshold voltage Transistors |
| title | Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T20%3A05%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Flash%20Memories:%20ISPP%20Renewal%20Theory%20and%20Flash%20Design%20Tradeoffs&rft.jtitle=IEEE%20journal%20on%20selected%20areas%20in%20communications&rft.au=Asadi,%20Meysam&rft.date=2016-09-01&rft.volume=34&rft.issue=9&rft.spage=2325&rft.epage=2335&rft.pages=2325-2335&rft.issn=0733-8716&rft.eissn=1558-0008&rft.coden=ISACEM&rft_id=info:doi/10.1109/JSAC.2016.2604058&rft_dat=%3Cproquest_RIE%3E4224054681%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1831025700&rft_id=info:pmid/&rft_ieee_id=7556371&rfr_iscdi=true |