Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (V t ) sh...

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Veröffentlicht in:	IEEE transactions on electron devices 2016-03, Vol.63 (3), p.1047-1053
Hauptverfasser:	Yeh, Teng-Hao Elton, Wei-Chen Chen, Hsu, Tzu-Hsuan Bruce, Du, Pei-Ying Penny, Chih-Chang Hsieh, Hang-Ting Lue, Yen-Hao Shih, Ya-Chin King, Chih-Yuan Lu
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithm design and analysis Arrays Channels Couplings Density Electric potential Guidelines Logic gates Optimization Programming Silicon Three dimensional Vertical gate (VG)-type 3-D NAND flash Z-disturbance Z-interference
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