Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND
In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (V t ) sh...
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| Veröffentlicht in: | IEEE transactions on electron devices 2016-03, Vol.63 (3), p.1047-1053 |
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| creator | Yeh, Teng-Hao Elton Wei-Chen Chen Hsu, Tzu-Hsuan Bruce Du, Pei-Ying Penny Chih-Chang Hsieh Hang-Ting Lue Yen-Hao Shih Ya-Chin King Chih-Yuan Lu |
| description | In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (V t ) shift due to two unique mechanisms. The first mechanism is the fringing field of the programmed charges (Z-interference), whereas the second one is the degraded inhibited potential affected by the programmed PL channel, which is grounded (Z-disturbance). Z-interference happens before Z-disturbance, so it is more critical to the memory window. Optimizing PL/OX thickness or engineering the PL sidewall profile can balance the constraint of Z-interference and the demand of higher memory density. They are important guidelines when designing VG-type 3-D NAND memory. |
| doi_str_mv | 10.1109/TED.2016.2520965 |
| format | Article |
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| subjects | Algorithm design and analysis Arrays Channels Couplings Density Electric potential Guidelines Logic gates Optimization Programming Silicon Three dimensional Vertical gate (VG)-type 3-D NAND flash Z-disturbance Z-interference |
| title | Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND |
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