A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang-bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition den...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2016-02, Vol.51 (2), p.428-439
Hauptverfasser:	Guanghua Shu, Woo-Seok Choi, Saxena, Saurabh, Talegaonkar, Mrunmay, Anand, Tejasvi, Elkholy, Ahmed, Elshazly, Amr, Hanumolu, Pavan Kumar
Format:	Artikel
Sprache:	eng
Schlagworte:	Active repeater automatic frequency acquisition Automatic frequency control continuous-rate receivers decouple jitter transfer (JTRAN)/jitter generation (JGEN) decouple JTRAN/jitter tolerance (JTOL) Detectors digital clock and data recovery (CDR) fractional-N phase-locked loop (PLL) Frequency locked loops high-speed serial link Jitter jitter peaking multiplying delay-locked loop optical links Oscillators Phase locked loops reference-less frequency-locked loop supply regulator wide-range digitally controlled oscillator (DCO)
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