SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations

Field-programmable gate arrays are becoming one of the implementation platforms of choice for computationally intensive embedded applications, such as multimode stream processors; such systems often exhibit poor cost-efficiency as various system modules can be idle, based on operating mode. This problem can be addressed through the use of reconfigurable computing, which allows underlying logic resources to be shared among system modules; using this approach, an application and mode specific processor can be generated at run-time. However, this generation process can interfere with application workloads; this is particularly true in the case of high data-rate stream processors. To address this problem, this brief presents a system-on-programmable-chip self-integration mechanism aimed at reconfigurable stream processors. The proposed mechanism is implemented using a distributed architecture and the multimode adaptive collaborative reconfigurable self-organized system framework. The mechanism arranges configuration, link establishment, and scheduling tasks around the stream workload, which allows for seamless run-time architecture adaptation. When compared with traditional approaches, based on central, instruction-based sequential processors, the proposed approach is shown to offer a faster (up to 10 times) link establishment and the scheduling capabilities; more importantly, the proposed mechanism can offer seamless run-time architecture adaptation by allowing the overlap of processing and configuration tasks.