A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology
This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output com...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2015-08, Vol.50 (8), p.1903-1916 |
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| container_end_page | 1916 |
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| container_issue | 8 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 50 |
| creator | Ming-Shuan Chen Yang, Chih-Kong Ken |
| description | This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output combiner reduces the required number of inductors and hence reduces the area. In addition, a novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power. Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit. |
| doi_str_mv | 10.1109/JSSC.2015.2411625 |
| format | Article |
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Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2015.2411625</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bandwidth ; Capacitance ; Circuits ; Clocks ; CMOS ; Delay lines ; Delays ; Equalizers ; feedforward equalizer (FFE) ; High speed ; Inductors ; LC-ladder filter ; multiplexer ; Multiplexing ; serial link ; serializer ; transmitter ; Transmitters</subject><ispartof>IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1903-1916</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2015</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c466t-939d57a1751717db3bc6bbc30760b1242348283b4f490d127d7329013d5a880d3</citedby><cites>FETCH-LOGICAL-c466t-939d57a1751717db3bc6bbc30760b1242348283b4f490d127d7329013d5a880d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7086344$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7086344$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ming-Shuan Chen</creatorcontrib><creatorcontrib>Yang, Chih-Kong Ken</creatorcontrib><title>A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap equalizer. 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Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.</description><subject>Bandwidth</subject><subject>Capacitance</subject><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Delay lines</subject><subject>Delays</subject><subject>Equalizers</subject><subject>feedforward equalizer (FFE)</subject><subject>High speed</subject><subject>Inductors</subject><subject>LC-ladder filter</subject><subject>multiplexer</subject><subject>Multiplexing</subject><subject>serial link</subject><subject>serializer</subject><subject>transmitter</subject><subject>Transmitters</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkD1PIzEQhi10SOSAH4BoLF1DgYPH3y5hRbhDQRQJgs7yrh0w2uzm7E0Bv56Ngq64ajSa5301ehA6AzoFoPbqfrGopoyCnDIBoJg8QBOQ0hDQ_OUHmlAKhlhG6RH6Wcr7uAphYIJW11hSogS-q68KXsScfJs-U_eKl9l3ZZ2GIWb8nIY37LEgS7-5xPOKzH0IMZNZasczufElBjyb3eLUYSVxt8bVw-MCL2Pz1vVt__pxgg5Xvi3x9Hseo6fZ7bL6TeaPd3-q6zlphFIDsdwGqT1oCRp0qHndqLpuONWK1sAE48Iww2uxEpYGYDpoziwFHqQ3hgZ-jC72vZvc_93GMrh1Kk1sW9_FflvcWGssAxBmRH_9h77329yN3zlQ1o7_gNAjBXuqyX0pOa7cJqe1zx8OqNuZdzvzbmfefZsfM-f7TIox_uM1NYoLwb8Az8V5FQ</recordid><startdate>20150801</startdate><enddate>20150801</enddate><creator>Ming-Shuan Chen</creator><creator>Yang, Chih-Kong Ken</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| ispartof | IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1903-1916 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Bandwidth Capacitance Circuits Clocks CMOS Delay lines Delays Equalizers feedforward equalizer (FFE) High speed Inductors LC-ladder filter multiplexer Multiplexing serial link serializer transmitter Transmitters |
| title | A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology |
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