Realization of low contact resistance close to theoretical limit in graphene transistors
Realizing low contact resistance between graphene and metal electrodes remains a well-known challenge for building high-performance graphene devices. In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal...
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| Veröffentlicht in: | Nano research 2015-05, Vol.8 (5), p.1669-1679 |
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| creator | Zhong, Hua Zhang, Zhiyong Chen, Bingyan Xu, Haitao Yu, Dangming Huang, Le Peng, Lianmao |
| description | Realizing low contact resistance between graphene and metal electrodes remains a well-known challenge for building high-performance graphene devices. In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal contacts. The Pd/graphene contact resistance at room temperature is reduced below the 100 Ω·μm level both on mechanically exfoliated and chemical-vapor-deposition graphene by adopting high-purity palladium and high-quality graphene and controlling the fabrication process to not contaminate the interface. After excluding the parasitic series resistances from the measurement system and electrodes, the retrieved contact resistance is shown to be systematically and statistically less than 100 Ω·μm, with a minimum value of 69 Ω·μm, which is very close to the theoretical limit. Furthermore, the contact resistance shows no clear dependence on temperature in the range of 77-300 K; this is attributed to the saturation of carrier injection efficiency between graphene and Pd owing to the high quality of the graphene samples used, which have a sufficiently long carrier mean-free-path. |
| doi_str_mv | 10.1007/s12274-014-0656-z |
| format | Article |
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In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal contacts. The Pd/graphene contact resistance at room temperature is reduced below the 100 Ω·μm level both on mechanically exfoliated and chemical-vapor-deposition graphene by adopting high-purity palladium and high-quality graphene and controlling the fabrication process to not contaminate the interface. After excluding the parasitic series resistances from the measurement system and electrodes, the retrieved contact resistance is shown to be systematically and statistically less than 100 Ω·μm, with a minimum value of 69 Ω·μm, which is very close to the theoretical limit. Furthermore, the contact resistance shows no clear dependence on temperature in the range of 77-300 K; this is attributed to the saturation of carrier injection efficiency between graphene and Pd owing to the high quality of the graphene samples used, which have a sufficiently long carrier mean-free-path.</description><identifier>ISSN: 1998-0124</identifier><identifier>EISSN: 1998-0000</identifier><identifier>DOI: 10.1007/s12274-014-0656-z</identifier><language>eng</language><publisher>Beijing: Tsinghua University Press</publisher><subject>Atomic/Molecular Structure and Spectra ; Biomedicine ; Biotechnology ; Chemistry and Materials Science ; Condensed Matter Physics ; Efficiency ; Electrodes ; Fabrication ; Graphene ; Materials Science ; Metals ; Nanotechnology ; Palladium ; Research Article ; Transistors ; 化学气相沉积 ; 平均自由程 ; 接触电阻 ; 晶体管 ; 测量系统 ; 理论极限 ; 石墨 ; 金属电极</subject><ispartof>Nano research, 2015-05, Vol.8 (5), p.1669-1679</ispartof><rights>Tsinghua University Press and Springer-Verlag Berlin Heidelberg 2014</rights><rights>Tsinghua University Press and Springer-Verlag Berlin Heidelberg 2015</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c479t-b86e4c055175ef1ab34154f681e6cbadfb68ae6c79b092b49fa6c6ebf7c99263</citedby><cites>FETCH-LOGICAL-c479t-b86e4c055175ef1ab34154f681e6cbadfb68ae6c79b092b49fa6c6ebf7c99263</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Uhttp://image.cqvip.com/vip1000/qk/71233X/71233X.jpg</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s12274-014-0656-z$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s12274-014-0656-z$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>314,776,780,27901,27902,41464,42533,51294</link.rule.ids></links><search><creatorcontrib>Zhong, Hua</creatorcontrib><creatorcontrib>Zhang, Zhiyong</creatorcontrib><creatorcontrib>Chen, Bingyan</creatorcontrib><creatorcontrib>Xu, Haitao</creatorcontrib><creatorcontrib>Yu, Dangming</creatorcontrib><creatorcontrib>Huang, Le</creatorcontrib><creatorcontrib>Peng, Lianmao</creatorcontrib><title>Realization of low contact resistance close to theoretical limit in graphene transistors</title><title>Nano research</title><addtitle>Nano Res</addtitle><addtitle>Nano Research</addtitle><description>Realizing low contact resistance between graphene and metal electrodes remains a well-known challenge for building high-performance graphene devices. In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal contacts. The Pd/graphene contact resistance at room temperature is reduced below the 100 Ω·μm level both on mechanically exfoliated and chemical-vapor-deposition graphene by adopting high-purity palladium and high-quality graphene and controlling the fabrication process to not contaminate the interface. After excluding the parasitic series resistances from the measurement system and electrodes, the retrieved contact resistance is shown to be systematically and statistically less than 100 Ω·μm, with a minimum value of 69 Ω·μm, which is very close to the theoretical limit. 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research</jtitle><stitle>Nano Res</stitle><addtitle>Nano Research</addtitle><date>2015-05-01</date><risdate>2015</risdate><volume>8</volume><issue>5</issue><spage>1669</spage><epage>1679</epage><pages>1669-1679</pages><issn>1998-0124</issn><eissn>1998-0000</eissn><abstract>Realizing low contact resistance between graphene and metal electrodes remains a well-known challenge for building high-performance graphene devices. In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal contacts. The Pd/graphene contact resistance at room temperature is reduced below the 100 Ω·μm level both on mechanically exfoliated and chemical-vapor-deposition graphene by adopting high-purity palladium and high-quality graphene and controlling the fabrication process to not contaminate the interface. After excluding the parasitic series resistances from the measurement system and electrodes, the retrieved contact resistance is shown to be systematically and statistically less than 100 Ω·μm, with a minimum value of 69 Ω·μm, which is very close to the theoretical limit. Furthermore, the contact resistance shows no clear dependence on temperature in the range of 77-300 K; this is attributed to the saturation of carrier injection efficiency between graphene and Pd owing to the high quality of the graphene samples used, which have a sufficiently long carrier mean-free-path.</abstract><cop>Beijing</cop><pub>Tsinghua University Press</pub><doi>10.1007/s12274-014-0656-z</doi><tpages>11</tpages></addata></record> |
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| identifier | ISSN: 1998-0124 |
| ispartof | Nano research, 2015-05, Vol.8 (5), p.1669-1679 |
| issn | 1998-0124 1998-0000 |
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| subjects | Atomic/Molecular Structure and Spectra Biomedicine Biotechnology Chemistry and Materials Science Condensed Matter Physics Efficiency Electrodes Fabrication Graphene Materials Science Metals Nanotechnology Palladium Research Article Transistors 化学气相沉积 平均自由程 接触电阻 晶体管 测量系统 理论极限 石墨 金属电极 |
| title | Realization of low contact resistance close to theoretical limit in graphene transistors |
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