A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology
In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability...
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| Veröffentlicht in: | IEEE transactions on electron devices 2014-12, Vol.61 (12), p.3991-3999 |
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| container_title | IEEE transactions on electron devices |
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| creator | El Husseini, Joanna Garros, Xavier Cluzel, Jacques Subirats, Alexandre Makosiej, Adam Weber, Olivier Thomas, Olivier Huard, Vincent Federspiel, Xavier Reimbold, Gilles |
| description | In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages V DD . The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work. |
| doi_str_mv | 10.1109/TED.2014.2361954 |
| format | Article |
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This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages V DD . The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2014.2361954</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bias temperature instability (BTI) stress measurements ; BTI stress modeling ; Random access memory ; read failure probability evaluation ; SRAM cells ; static random access memory (SRAM) cells ; Stress ; Stress measurement ; supply read retention voltage (SRRV) metric ; Transistors ; Voltage measurement</subject><ispartof>IEEE transactions on electron devices, 2014-12, Vol.61 (12), p.3991-3999</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Dec 2014</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c427t-d0bc9da7e5431bd774115c8ae1725568e452b3dec80d9e8862faafe7e8d39bb93</citedby><cites>FETCH-LOGICAL-c427t-d0bc9da7e5431bd774115c8ae1725568e452b3dec80d9e8862faafe7e8d39bb93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6930752$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6930752$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>El Husseini, Joanna</creatorcontrib><creatorcontrib>Garros, Xavier</creatorcontrib><creatorcontrib>Cluzel, Jacques</creatorcontrib><creatorcontrib>Subirats, Alexandre</creatorcontrib><creatorcontrib>Makosiej, Adam</creatorcontrib><creatorcontrib>Weber, Olivier</creatorcontrib><creatorcontrib>Thomas, Olivier</creatorcontrib><creatorcontrib>Huard, Vincent</creatorcontrib><creatorcontrib>Federspiel, Xavier</creatorcontrib><creatorcontrib>Reimbold, Gilles</creatorcontrib><title>A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages V DD . The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.</description><subject>Bias temperature instability (BTI) stress measurements</subject><subject>BTI stress modeling</subject><subject>Random access memory</subject><subject>read failure probability evaluation</subject><subject>SRAM cells</subject><subject>static random access memory (SRAM) cells</subject><subject>Stress</subject><subject>Stress measurement</subject><subject>supply read retention voltage (SRRV) metric</subject><subject>Transistors</subject><subject>Voltage measurement</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtLI0EUhYthhMmo-wE3BbPuWO_HMiY6E1AEjbNtqqtum5JOVaa6s2h_vR0iri4HvnMufAj9omROKbHXm9vVnBEq5owraqX4hmZUSl1ZJdR3NCOEmspyw3-gn33_NkUlBJuhcYGXebfvYAC83Lri_AAlvrsh5oRdCvghB-hiesW5xcMW8M1mXa1TOHgIeDUmt4se_3MluiZ2cRiP2PPT4gEvSnFjj2PCzFRph-9W1fPjGm_Ab1Pu8ut4gc5a1_Vw-XnP0cvd7Wb5t7p__LNeLu4rL5geqkAab4PTIAWnTdBaUCq9cUA1k1IZEJI1PIA3JFgwRrHWuRY0mMBt01h-jn6fdvcl_z9AP9Rv-VDS9LKmimujhCZyosiJ8iX3fYG23pe4c2WsKamPgutJcH0UXH8KnipXp0oEgC9cWU60ZPwD3Ox1yg</recordid><startdate>20141201</startdate><enddate>20141201</enddate><creator>El Husseini, Joanna</creator><creator>Garros, Xavier</creator><creator>Cluzel, Jacques</creator><creator>Subirats, Alexandre</creator><creator>Makosiej, Adam</creator><creator>Weber, Olivier</creator><creator>Thomas, Olivier</creator><creator>Huard, Vincent</creator><creator>Federspiel, Xavier</creator><creator>Reimbold, Gilles</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages V DD . The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2014.2361954</doi><tpages>9</tpages></addata></record> |
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| subjects | Bias temperature instability (BTI) stress measurements BTI stress modeling Random access memory read failure probability evaluation SRAM cells static random access memory (SRAM) cells Stress Stress measurement supply read retention voltage (SRRV) metric Transistors Voltage measurement |
| title | A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology |
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