A Survey of High-level Synthesis Languages and Synthesizers for FPGAs

Due to available of large FPGAs, FPGAs are used for implementing not only simple hardware logics, but also complicated algorithms. By the reason, FPGAs are pointed out as execution platforms of program. Although RLT design is widely used for development hardware logic on FPGA, the RTL design for a complicated algorithm is an inconvenient and time-consuming approach. Therefore, high-level synthesis languages (HLSLs) are desired to design hardware in a higher abstraction level than RTL. HLSLs are needed to ease hardware design, to decrease verification, and to exploit the performance of the FPGA. This paper surveys HLSLs and high-level synthesizers.