A Class-F CMOS Oscillator

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of -136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm 2 while drawing 12 mA from 1.25 V supply.