Data Transmission Hardware Design of IPv6 Node for Internet of Things

To reduce the resource consumption in traditional software IPv6 Internet protocols based on embedded system, a data transmission hardware scenario of reduced IPv6 protocol with optimized cache structures based on the FPGA is designed using Verilog HDL. This scenario implements the function of the Tr...

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Veröffentlicht in:	Applied Mechanics and Materials 2013-07, Vol.336-338, p.2494-2499
Hauptverfasser:	Tan, Hong Zhou, Chen, Rong Jun, Xie, Shun Dao, Zhu, Xiong Yong, Xie, Kai
Format:	Artikel
Sprache:	eng
Schlagworte:	Internet of Things
Online-Zugang:	Volltext
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