MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor
This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel d...
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| Veröffentlicht in: | IEEE transactions on circuits and systems for video technology 2013-10, Vol.23 (10), p.1767-1780 |
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| container_title | IEEE transactions on circuits and systems for video technology |
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| creator | Kim, Sung Dae Sunwoo, Myung Hoon |
| description | This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203 K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation. |
| doi_str_mv | 10.1109/TCSVT.2013.2268992 |
| format | Article |
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The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203 K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation.</description><identifier>ISSN: 1051-8215</identifier><identifier>EISSN: 1558-2205</identifier><identifier>DOI: 10.1109/TCSVT.2013.2268992</identifier><identifier>CODEN: ITCTEM</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Algorithms ; Application-specific instruction-set processor (ASIP) ; Applied sciences ; Arrays ; Circuits ; CMOS ; Computer simulation ; configurable architecture ; Design. Technologies. Operation analysis. Testing ; Detection, estimation, filtering, equalization, prediction ; Electronics ; Exact sciences and technology ; Image processing ; Information, signal and communications theory ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Loading ; low-power design ; Microprocessors ; Motion estimation ; motion estimation/motion compensation (ME/MC) ; Motion simulation ; Prediction algorithms ; Redundant ; Registers ; search scan order ; Searching ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal and communications theory ; Signal processing ; Signal processing algorithms ; Signal, noise ; Studies ; Telecommunications and information theory</subject><ispartof>IEEE transactions on circuits and systems for video technology, 2013-10, Vol.23 (10), p.1767-1780</ispartof><rights>2014 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Oct 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c358t-2bc9293d4a4d649478efef2ca5d9825e594279bc61dedafe551b03519ef143b93</citedby><cites>FETCH-LOGICAL-c358t-2bc9293d4a4d649478efef2ca5d9825e594279bc61dedafe551b03519ef143b93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6532339$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6532339$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=27836719$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kim, Sung Dae</creatorcontrib><creatorcontrib>Sunwoo, Myung Hoon</creatorcontrib><title>MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor</title><title>IEEE transactions on circuits and systems for video technology</title><addtitle>TCSVT</addtitle><description>This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203 K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation.</description><subject>Algorithms</subject><subject>Application-specific instruction-set processor (ASIP)</subject><subject>Applied sciences</subject><subject>Arrays</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Computer simulation</subject><subject>configurable architecture</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Detection, estimation, filtering, equalization, prediction</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Image processing</subject><subject>Information, signal and communications theory</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Loading</subject><subject>low-power design</subject><subject>Microprocessors</subject><subject>Motion estimation</subject><subject>motion estimation/motion compensation (ME/MC)</subject><subject>Motion simulation</subject><subject>Prediction algorithms</subject><subject>Redundant</subject><subject>Registers</subject><subject>search scan order</subject><subject>Searching</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal and communications theory</subject><subject>Signal processing</subject><subject>Signal processing algorithms</subject><subject>Signal, noise</subject><subject>Studies</subject><subject>Telecommunications and information theory</subject><issn>1051-8215</issn><issn>1558-2205</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE9r3DAQxUVIIcm2X6C5GEIhF281I8m2egvbbbuQkJDd9hQQsjwKDo61lexDvn29f8ihp3nMvBne_Bj7DHwOwPXXzWL9ZzNHDmKOWFRa4wk7B6WqHJGr00lzBXmFoM7YRUovnIOsZHnOnu6W69XDt-wmW4Tet89jtHVHme2b7LsdbPZIY9p37sLQhj5bpqF9tXu53pJrfeuyVZ-GOLpdM1_TkD3E4CilED-yD952iT4d64z9_rHcLH7lt_c_V4ub29wJVQ051k6jFo20simklmVFnjw6qxpdoSKlJZa6dgU01FhPSkHNhQJNHqSotZix68PdbQx_R0qDeW2To66zPYUxGShKUDBh4ZP16j_rSxhjP6UzICXniGqCOGN4cLkYUorkzTZOb8c3A9zsgJs9cLMDbo7Ap6Uvx9M2Odv5aHvXpvdNLCsx5dilvTz4WiJ6HxdKoBBa_AOzI4h4</recordid><startdate>20131001</startdate><enddate>20131001</enddate><creator>Kim, Sung Dae</creator><creator>Sunwoo, Myung Hoon</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20131001</creationdate><title>MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor</title><author>Kim, Sung Dae ; Sunwoo, Myung Hoon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c358t-2bc9293d4a4d649478efef2ca5d9825e594279bc61dedafe551b03519ef143b93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Algorithms</topic><topic>Application-specific instruction-set processor (ASIP)</topic><topic>Applied sciences</topic><topic>Arrays</topic><topic>Circuits</topic><topic>CMOS</topic><topic>Computer simulation</topic><topic>configurable architecture</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Detection, estimation, filtering, equalization, prediction</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Image processing</topic><topic>Information, signal and communications theory</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Loading</topic><topic>low-power design</topic><topic>Microprocessors</topic><topic>Motion estimation</topic><topic>motion estimation/motion compensation (ME/MC)</topic><topic>Motion simulation</topic><topic>Prediction algorithms</topic><topic>Redundant</topic><topic>Registers</topic><topic>search scan order</topic><topic>Searching</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal and communications theory</topic><topic>Signal processing</topic><topic>Signal processing algorithms</topic><topic>Signal, noise</topic><topic>Studies</topic><topic>Telecommunications and information theory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kim, Sung Dae</creatorcontrib><creatorcontrib>Sunwoo, Myung Hoon</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on circuits and systems for video technology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kim, Sung Dae</au><au>Sunwoo, Myung Hoon</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor</atitle><jtitle>IEEE transactions on circuits and systems for video technology</jtitle><stitle>TCSVT</stitle><date>2013-10-01</date><risdate>2013</risdate><volume>23</volume><issue>10</issue><spage>1767</spage><epage>1780</epage><pages>1767-1780</pages><issn>1051-8215</issn><eissn>1558-2205</eissn><coden>ITCTEM</coden><abstract>This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203 K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TCSVT.2013.2268992</doi><tpages>14</tpages></addata></record> |
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| subjects | Algorithms Application-specific instruction-set processor (ASIP) Applied sciences Arrays Circuits CMOS Computer simulation configurable architecture Design. Technologies. Operation analysis. Testing Detection, estimation, filtering, equalization, prediction Electronics Exact sciences and technology Image processing Information, signal and communications theory Integrated circuits Integrated circuits by function (including memories and processors) Loading low-power design Microprocessors Motion estimation motion estimation/motion compensation (ME/MC) Motion simulation Prediction algorithms Redundant Registers search scan order Searching Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal and communications theory Signal processing Signal processing algorithms Signal, noise Studies Telecommunications and information theory |
| title | MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor |
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