Light-Load Efficiency Improvement in Buck-Derived Single-Stage Single-Switch PFC Converters
Single-stage single-switch ac/dc converters with power factor correction (PFC) generally have higher power losses under a light-load condition, as compared to that of the two-stage approach, due to the sharing of a common power transistor such that the PFC stage cannot be switched OFF separately to...
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Veröffentlicht in: | IEEE transactions on power electronics 2013-05, Vol.28 (5), p.2105-2110 |
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description | Single-stage single-switch ac/dc converters with power factor correction (PFC) generally have higher power losses under a light-load condition, as compared to that of the two-stage approach, due to the sharing of a common power transistor such that the PFC stage cannot be switched OFF separately to save power losses. This letter addresses this problem by using a buck topology for the PFC stage of the single-stage single-switch converters as it can be completely turned OFF by operating the converter only near the zero crossing of the input voltage, due to the presence of the dead angle of input current. Hence, the switching and conduction losses to the transistor and diodes, and passive devices are reduced. Also, further improvement is made by finding the best combination of dc-bus capacitor charging time and discharging time to achieve the lowest power loss. A recently proposed converter topology which combines a buck PFC cell with a buck-boost dc/dc cell is used as an example. Experimental results are reported and confirmed that the proposed light-load power loss reduction scheme on the converter can improve power stage efficiency by up to 7% at 1 W of output power as compared to that without the proposed scheme. |
doi_str_mv | 10.1109/TPEL.2012.2221744 |
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D-C ; Shu-Kong Ki</creator><creatorcontrib>Lu, D. D-C ; Shu-Kong Ki</creatorcontrib><description>Single-stage single-switch ac/dc converters with power factor correction (PFC) generally have higher power losses under a light-load condition, as compared to that of the two-stage approach, due to the sharing of a common power transistor such that the PFC stage cannot be switched OFF separately to save power losses. This letter addresses this problem by using a buck topology for the PFC stage of the single-stage single-switch converters as it can be completely turned OFF by operating the converter only near the zero crossing of the input voltage, due to the presence of the dead angle of input current. Hence, the switching and conduction losses to the transistor and diodes, and passive devices are reduced. Also, further improvement is made by finding the best combination of dc-bus capacitor charging time and discharging time to achieve the lowest power loss. A recently proposed converter topology which combines a buck PFC cell with a buck-boost dc/dc cell is used as an example. Experimental results are reported and confirmed that the proposed light-load power loss reduction scheme on the converter can improve power stage efficiency by up to 7% at 1 W of output power as compared to that without the proposed scheme.</description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2012.2221744</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Capacitors ; Circuit properties ; Connection and protection apparatus ; Diodes ; Electric currents ; Electric, optical and optoelectronic circuits ; Electrical engineering. Electrical power engineering ; Electronic circuits ; Electronics ; Exact sciences and technology ; Light-load efficiency ; Logic gates ; MOSFET circuits ; power consumption ; Power electronics, power supplies ; Power factor correction ; Power supply ; Pulse width modulation ; Signal convertors ; single-stage ; Switches ; Switching loss ; Switching, multiplexing, switched capacity circuits ; Topology ; Transistors ; Voltage control</subject><ispartof>IEEE transactions on power electronics, 2013-05, Vol.28 (5), p.2105-2110</ispartof><rights>2014 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) May 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c323t-675dc4dddc6a8528817aed3c75426f3b549b4daa55cbcf463a3898dbee9ec9cd3</citedby><cites>FETCH-LOGICAL-c323t-675dc4dddc6a8528817aed3c75426f3b549b4daa55cbcf463a3898dbee9ec9cd3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6319416$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6319416$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=27251787$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Lu, D. D-C</creatorcontrib><creatorcontrib>Shu-Kong Ki</creatorcontrib><title>Light-Load Efficiency Improvement in Buck-Derived Single-Stage Single-Switch PFC Converters</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description>Single-stage single-switch ac/dc converters with power factor correction (PFC) generally have higher power losses under a light-load condition, as compared to that of the two-stage approach, due to the sharing of a common power transistor such that the PFC stage cannot be switched OFF separately to save power losses. This letter addresses this problem by using a buck topology for the PFC stage of the single-stage single-switch converters as it can be completely turned OFF by operating the converter only near the zero crossing of the input voltage, due to the presence of the dead angle of input current. Hence, the switching and conduction losses to the transistor and diodes, and passive devices are reduced. Also, further improvement is made by finding the best combination of dc-bus capacitor charging time and discharging time to achieve the lowest power loss. A recently proposed converter topology which combines a buck PFC cell with a buck-boost dc/dc cell is used as an example. Experimental results are reported and confirmed that the proposed light-load power loss reduction scheme on the converter can improve power stage efficiency by up to 7% at 1 W of output power as compared to that without the proposed scheme.</description><subject>Applied sciences</subject><subject>Capacitors</subject><subject>Circuit properties</subject><subject>Connection and protection apparatus</subject><subject>Diodes</subject><subject>Electric currents</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electrical engineering. Electrical power engineering</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Light-load efficiency</subject><subject>Logic gates</subject><subject>MOSFET circuits</subject><subject>power consumption</subject><subject>Power electronics, power supplies</subject><subject>Power factor correction</subject><subject>Power supply</subject><subject>Pulse width modulation</subject><subject>Signal convertors</subject><subject>single-stage</subject><subject>Switches</subject><subject>Switching loss</subject><subject>Switching, multiplexing, switched capacity circuits</subject><subject>Topology</subject><subject>Transistors</subject><subject>Voltage control</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kU9PwkAQxTdGExH9AMZLE-OxuH_b3aMiKEkTScCTh2a7O4VFaHG3YPj2toFwmkzm995M3iB0T_CAEKye59NRNqCY0AGllKScX6AeUZzEmOD0EvWwlCKWSrFrdBPCCmPCBSY99J25xbKJs1rbaFSWzjiozCGabLa-3sMGqiZyVfS6Mz_xG3i3BxvNXLVYQzxr9ALOzZ9rzDKajofRsK724Bvw4RZdlXod4O5U--hrPJoPP-Ls830yfMliwyhr4iQV1nBrrUm0FFRKkmqwzKSC06RkheCq4FZrIUxhSp4wzaSStgBQYJSxrI8ej77tzb87CE2-qne-alfmhFLGJWGKtRQ5UsbXIXgo8613G-0POcF5l2HeZZh3GeanDFvN08lZB6PXpdeVceEspCkVJJVpyz0cOQcA53HCug8k7B-U2np7</recordid><startdate>20130501</startdate><enddate>20130501</enddate><creator>Lu, D. D-C</creator><creator>Shu-Kong Ki</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope></search><sort><creationdate>20130501</creationdate><title>Light-Load Efficiency Improvement in Buck-Derived Single-Stage Single-Switch PFC Converters</title><author>Lu, D. D-C ; Shu-Kong Ki</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c323t-675dc4dddc6a8528817aed3c75426f3b549b4daa55cbcf463a3898dbee9ec9cd3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Applied sciences</topic><topic>Capacitors</topic><topic>Circuit properties</topic><topic>Connection and protection apparatus</topic><topic>Diodes</topic><topic>Electric currents</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electrical engineering. Electrical power engineering</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Light-load efficiency</topic><topic>Logic gates</topic><topic>MOSFET circuits</topic><topic>power consumption</topic><topic>Power electronics, power supplies</topic><topic>Power factor correction</topic><topic>Power supply</topic><topic>Pulse width modulation</topic><topic>Signal convertors</topic><topic>single-stage</topic><topic>Switches</topic><topic>Switching loss</topic><topic>Switching, multiplexing, switched capacity circuits</topic><topic>Topology</topic><topic>Transistors</topic><topic>Voltage control</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lu, D. D-C</creatorcontrib><creatorcontrib>Shu-Kong Ki</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on power electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lu, D. D-C</au><au>Shu-Kong Ki</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Light-Load Efficiency Improvement in Buck-Derived Single-Stage Single-Switch PFC Converters</atitle><jtitle>IEEE transactions on power electronics</jtitle><stitle>TPEL</stitle><date>2013-05-01</date><risdate>2013</risdate><volume>28</volume><issue>5</issue><spage>2105</spage><epage>2110</epage><pages>2105-2110</pages><issn>0885-8993</issn><eissn>1941-0107</eissn><coden>ITPEE8</coden><abstract>Single-stage single-switch ac/dc converters with power factor correction (PFC) generally have higher power losses under a light-load condition, as compared to that of the two-stage approach, due to the sharing of a common power transistor such that the PFC stage cannot be switched OFF separately to save power losses. This letter addresses this problem by using a buck topology for the PFC stage of the single-stage single-switch converters as it can be completely turned OFF by operating the converter only near the zero crossing of the input voltage, due to the presence of the dead angle of input current. Hence, the switching and conduction losses to the transistor and diodes, and passive devices are reduced. Also, further improvement is made by finding the best combination of dc-bus capacitor charging time and discharging time to achieve the lowest power loss. A recently proposed converter topology which combines a buck PFC cell with a buck-boost dc/dc cell is used as an example. Experimental results are reported and confirmed that the proposed light-load power loss reduction scheme on the converter can improve power stage efficiency by up to 7% at 1 W of output power as compared to that without the proposed scheme.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TPEL.2012.2221744</doi><tpages>6</tpages></addata></record> |
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subjects | Applied sciences Capacitors Circuit properties Connection and protection apparatus Diodes Electric currents Electric, optical and optoelectronic circuits Electrical engineering. Electrical power engineering Electronic circuits Electronics Exact sciences and technology Light-load efficiency Logic gates MOSFET circuits power consumption Power electronics, power supplies Power factor correction Power supply Pulse width modulation Signal convertors single-stage Switches Switching loss Switching, multiplexing, switched capacity circuits Topology Transistors Voltage control |
title | Light-Load Efficiency Improvement in Buck-Derived Single-Stage Single-Switch PFC Converters |
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