A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detail...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2011-01, Vol.46 (1), p.64-75
Hauptverfasser:	Barth, John, Nair, Kavita, Cao, Nianzheng, Plass, Don, Nelson, Erik, Hwang, Charlie, Fredeman, Gregory, Sperling, Michael, Mathews, Abraham, Kirihata, Toshiaki, Reohr, William R.
Format:	Artikel
Sprache:	eng
Schlagworte:	Amplifiers Applied sciences Arrays Circuit properties Couplings Dielectric, amorphous and glass solid devices DRAM Macro Dynamic random access memory Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics embedded DRAM Cache Exact sciences and technology High voltages Integrated circuits Integrated circuits by function (including memories and processors) Metals Microprocessors Random access memory Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices System-on-a-chip Transistors Voltage
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