An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization

MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The del...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2010-08, Vol.57 (8), p.2041-2052
Hauptverfasser:	Musa, Osman, Shams, Maitham
Format:	Artikel
Sprache:	eng
Schlagworte:	Automated optimization CMOS CMOS logic circuits CMOS technology Coupling circuits Delay Design automation Design optimization Gates Inverters Logic Logic design Logic gates Mathematical analysis Mathematical models Metal oxide semiconductors MOS current-mode logic (MCML) Optimization Semiconductor device modeling source-coupled logic
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