Investigation of Interface Trap Charges and Temperature on RF Performance with Noise Analysis for IoT Application of a Heterojunction Tunnel FET

A comprehensive study on various reliability issues of a tunnel field-effect transistor (TFET) is outlined in this chapter. The investigation of reliability issues is vital to ensure the optimum performance of a device. The impediments caused by the interface trap charge type, polarity and distribution in the vicinity of the device have hazardous effects on device performance which is presented in detail. Likewise, ambient temperature can cause variation in device characteristics, including various RF/analogue parameters. The investigation of RF figure of merits (FOMs) is essential to analyse the suitability of a device in analogue circuits. Furthermore, the different densities and polarity of interface trap charges (ITCs) also alter these RF FOMs behaviour. Moreover, electrical noise induced ITC with regard to density and their distribution is investigated to comment on the reliability of the device. Different components of electrical noise are observed to be prevalent at different frequencies. The possibility and methodology for applications of a TFET device in advanced analogue circuits have been discussed to benchmark TFETs in analogue circuit domain. Moreover, the emergence of nanoscale transistors has reflected upon the realization of low power memory circuits on Internet of Things (IoT) applications as their data processing unit. Hence, the study of various reliability factors of a TFET will ensure the design strategies to satisfy the noteworthy necessities of IoT applications. This chapter outlines a comprehensive study on various reliability issues of a tunnel field-effect transistor (TFET). The investigation of reliability issues is vital to ensure the optimum performance of a device. Scaling down of devices in recent times has also brought hindrance to the thermal budget due to dopant fluctuations in the regions of high doping. The Radio frequency (RF) characterization is an utmost requirement for investigating the calibre of a device in the analogue circuit domain. Even in any modern communication system, the minimum distortion in signals should be preserved to understand the suitability of a device for RF / analogue based applications, maintaining high speed. The design of an innovative TFET architecture accompanied by the investigation of its various reliability factors can be implemented in greater speed of memory and digital applications that appears as a key task for Internet of Things systems. The heterojunction TFET architectures present