On-chip wiring design challenges for Gigahertz operation: Interconnections-Addressing the Next Challenge of IC Technology. Part I: Integration and Packaging Trends
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| Veröffentlicht in: | Proceedings of the IEEE 2001, Vol.89 (4), p.529-555 |
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| container_issue | 4 |
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| container_title | Proceedings of the IEEE |
| container_volume | 89 |
| creator | DEUTSCH, Alina COTEUS, Paul W KOPCSAY, Gerard V SMITH, Howard H SUROVIC, Christopher W KRAUTER, Byron L EDELSTEIN, Daniel C RESTLE, Phillip J |
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| fulltext | fulltext |
| identifier | ISSN: 0018-9219 |
| ispartof | Proceedings of the IEEE, 2001, Vol.89 (4), p.529-555 |
| issn | 0018-9219 1558-2256 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_965825 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Computer-aided design of microcircuits layout and modeling Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Metallization, contacts, interconnects device isolation Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | On-chip wiring design challenges for Gigahertz operation: Interconnections-Addressing the Next Challenge of IC Technology. Part I: Integration and Packaging Trends |
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