An experimental 80-ns 1-Mbit DRAM with fast page operation

An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip si...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1985-10, Vol.20 (5), p.914-923
Hauptverfasser:	Kalter, H.L., Coppens, P.D., Ellis, W.F., Fifield, J.A., Kokoszka, D.J., Leasure, T.L., Miller, C.P., Nguyen, Q., Papritz, R.E., Patton, C.S., Poplawski, J.M., Tomashot, S.W., van der Hoeven, W.B.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Area measurement Delay DRAM chips Electronics Error analysis Exact sciences and technology MOS devices Plastic packaging Protection Random access memory Semiconductor device measurement Size measurement Storage and reproduction of information
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