An experimental 80-ns 1-Mbit DRAM with fast page operation
An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip si...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1985-10, Vol.20 (5), p.914-923 |
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| container_end_page | 923 |
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| container_issue | 5 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 20 |
| creator | Kalter, H.L. Coppens, P.D. Ellis, W.F. Fifield, J.A. Kokoszka, D.J. Leasure, T.L. Miller, C.P. Nguyen, Q. Papritz, R.E. Patton, C.S. Poplawski, J.M. Tomashot, S.W. van der Hoeven, W.B. |
| description | An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package. |
| doi_str_mv | 10.1109/JSSC.1985.1052415 |
| format | Article |
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The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.1985.1052415</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Area measurement ; Delay ; DRAM chips ; Electronics ; Error analysis ; Exact sciences and technology ; MOS devices ; Plastic packaging ; Protection ; Random access memory ; Semiconductor device measurement ; Size measurement ; Storage and reproduction of information</subject><ispartof>IEEE journal of solid-state circuits, 1985-10, Vol.20 (5), p.914-923</ispartof><rights>1986 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c393t-4e36e25c998ce27900d94d79f71e03aedf7c5f7c9012b4facfd8945369e293ae3</citedby><cites>FETCH-LOGICAL-c393t-4e36e25c998ce27900d94d79f71e03aedf7c5f7c9012b4facfd8945369e293ae3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1052415$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1052415$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=8535643$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kalter, H.L.</creatorcontrib><creatorcontrib>Coppens, P.D.</creatorcontrib><creatorcontrib>Ellis, W.F.</creatorcontrib><creatorcontrib>Fifield, J.A.</creatorcontrib><creatorcontrib>Kokoszka, D.J.</creatorcontrib><creatorcontrib>Leasure, T.L.</creatorcontrib><creatorcontrib>Miller, C.P.</creatorcontrib><creatorcontrib>Nguyen, Q.</creatorcontrib><creatorcontrib>Papritz, R.E.</creatorcontrib><creatorcontrib>Patton, C.S.</creatorcontrib><creatorcontrib>Poplawski, J.M.</creatorcontrib><creatorcontrib>Tomashot, S.W.</creatorcontrib><creatorcontrib>van der Hoeven, W.B.</creatorcontrib><title>An experimental 80-ns 1-Mbit DRAM with fast page operation</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.</description><subject>Applied sciences</subject><subject>Area measurement</subject><subject>Delay</subject><subject>DRAM chips</subject><subject>Electronics</subject><subject>Error analysis</subject><subject>Exact sciences and technology</subject><subject>MOS devices</subject><subject>Plastic packaging</subject><subject>Protection</subject><subject>Random access memory</subject><subject>Semiconductor device measurement</subject><subject>Size measurement</subject><subject>Storage and reproduction of information</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1985</creationdate><recordtype>article</recordtype><recordid>eNpNkE1LAzEQhoMoWKs_QLzkIN62ZvLRTbyV-k2LYBW8hTQ70ZV1t262qP_elC3iYRiGeeaFeQg5BjYCYOb8frGYjsBoNQKmuAS1QwaglM4gFy-7ZMAY6MxwxvbJQYzvaZRSw4BcTGqK3ytsyw-sO1dRzbI6Usjmy7Kjl4-TOf0quzcaXOzoyr0ibRLsurKpD8lecFXEo20fkufrq6fpbTZ7uLmbTmaZF0Z0mUQxRq68Mdojzw1jhZFFbkIOyITDIuRepTIM-FIG50OhjVRibJCbtBdDctbnrtrmc42xsx9l9FhVrsZmHS3XigNjPIHQg75tYmwx2FV6y7U_FpjdWLIbS3ZjyW4tpZvTbbiL3lWhdbUv49-hVkKNpUjYSY-ViPgvtg_5BbBubhk</recordid><startdate>198510</startdate><enddate>198510</enddate><creator>Kalter, H.L.</creator><creator>Coppens, P.D.</creator><creator>Ellis, W.F.</creator><creator>Fifield, J.A.</creator><creator>Kokoszka, D.J.</creator><creator>Leasure, T.L.</creator><creator>Miller, C.P.</creator><creator>Nguyen, Q.</creator><creator>Papritz, R.E.</creator><creator>Patton, C.S.</creator><creator>Poplawski, J.M.</creator><creator>Tomashot, S.W.</creator><creator>van der Hoeven, W.B.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>198510</creationdate><title>An experimental 80-ns 1-Mbit DRAM with fast page operation</title><author>Kalter, H.L. ; Coppens, P.D. ; Ellis, W.F. ; Fifield, J.A. ; Kokoszka, D.J. ; Leasure, T.L. ; Miller, C.P. ; Nguyen, Q. ; Papritz, R.E. ; Patton, C.S. ; Poplawski, J.M. ; Tomashot, S.W. ; van der Hoeven, W.B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c393t-4e36e25c998ce27900d94d79f71e03aedf7c5f7c9012b4facfd8945369e293ae3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1985</creationdate><topic>Applied sciences</topic><topic>Area measurement</topic><topic>Delay</topic><topic>DRAM chips</topic><topic>Electronics</topic><topic>Error analysis</topic><topic>Exact sciences and technology</topic><topic>MOS devices</topic><topic>Plastic packaging</topic><topic>Protection</topic><topic>Random access memory</topic><topic>Semiconductor device measurement</topic><topic>Size measurement</topic><topic>Storage and reproduction of information</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kalter, H.L.</creatorcontrib><creatorcontrib>Coppens, P.D.</creatorcontrib><creatorcontrib>Ellis, W.F.</creatorcontrib><creatorcontrib>Fifield, J.A.</creatorcontrib><creatorcontrib>Kokoszka, D.J.</creatorcontrib><creatorcontrib>Leasure, T.L.</creatorcontrib><creatorcontrib>Miller, C.P.</creatorcontrib><creatorcontrib>Nguyen, Q.</creatorcontrib><creatorcontrib>Papritz, R.E.</creatorcontrib><creatorcontrib>Patton, C.S.</creatorcontrib><creatorcontrib>Poplawski, J.M.</creatorcontrib><creatorcontrib>Tomashot, S.W.</creatorcontrib><creatorcontrib>van der Hoeven, W.B.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kalter, H.L.</au><au>Coppens, P.D.</au><au>Ellis, W.F.</au><au>Fifield, J.A.</au><au>Kokoszka, D.J.</au><au>Leasure, T.L.</au><au>Miller, C.P.</au><au>Nguyen, Q.</au><au>Papritz, R.E.</au><au>Patton, C.S.</au><au>Poplawski, J.M.</au><au>Tomashot, S.W.</au><au>van der Hoeven, W.B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An experimental 80-ns 1-Mbit DRAM with fast page operation</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1985-10</date><risdate>1985</risdate><volume>20</volume><issue>5</issue><spage>914</spage><epage>923</epage><pages>914-923</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.1985.1052415</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1985-10, Vol.20 (5), p.914-923 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_pascalfrancis_primary_8535643 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Area measurement Delay DRAM chips Electronics Error analysis Exact sciences and technology MOS devices Plastic packaging Protection Random access memory Semiconductor device measurement Size measurement Storage and reproduction of information |
| title | An experimental 80-ns 1-Mbit DRAM with fast page operation |
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