Universal HSPICE macromodel for giant magnetoresistance memory bits
Nonvolatile semiconductor storage using giant magnetoresistance (GMR) memory bits has the potential for revolutionizing both high-density and high-speed memory applications with devices exhibiting unlimited write endurance and very low write energy. This paper presents the first universal circuit ma...
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Veröffentlicht in: | IEEE transactions on magnetics 2000-07, Vol.36 (4), p.2062-2072 |
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container_title | IEEE transactions on magnetics |
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creator | Das, B. Black, W.C. Pohm, A.V. |
description | Nonvolatile semiconductor storage using giant magnetoresistance (GMR) memory bits has the potential for revolutionizing both high-density and high-speed memory applications with devices exhibiting unlimited write endurance and very low write energy. This paper presents the first universal circuit macromodel for GMR memory bits. The macromodel is realized as a four-terminal subcircuit that emulates GMR bit behavior over a wide range of sense and word-line currents. It realistically models the nonlinear and hysteretic behavior of GMR memory bits, their transient thermal behavior, and the sense-current dependency of their write thresholds. The model is flexible and relatively simple: Ranges of the write/read currents and bit resistance values are incorporated as parameterized variables, and no semiconductor devices are used within the model. |
doi_str_mv | 10.1109/20.875339 |
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This paper presents the first universal circuit macromodel for GMR memory bits. The macromodel is realized as a four-terminal subcircuit that emulates GMR bit behavior over a wide range of sense and word-line currents. It realistically models the nonlinear and hysteretic behavior of GMR memory bits, their transient thermal behavior, and the sense-current dependency of their write thresholds. The model is flexible and relatively simple: Ranges of the write/read currents and bit resistance values are incorporated as parameterized variables, and no semiconductor devices are used within the model.</description><identifier>ISSN: 0018-9464</identifier><identifier>EISSN: 1941-0069</identifier><identifier>DOI: 10.1109/20.875339</identifier><identifier>CODEN: IEMGAQ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Antiferromagnetic materials ; Applied sciences ; Circuits ; Decoding ; Electronics ; Endurance ; Energy use ; Exact sciences and technology ; Giant magnetoresistance ; High speed ; Hysteresis ; Magnetic device characterization, design, and modeling ; Magnetic devices ; Magnetic fields ; Magnetic materials ; Magnetic separation ; Magnetic switching ; Magnetism ; Material storage ; Mathematical models ; Semiconductor electronics. Microelectronics. Optoelectronics. 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This paper presents the first universal circuit macromodel for GMR memory bits. The macromodel is realized as a four-terminal subcircuit that emulates GMR bit behavior over a wide range of sense and word-line currents. It realistically models the nonlinear and hysteretic behavior of GMR memory bits, their transient thermal behavior, and the sense-current dependency of their write thresholds. The model is flexible and relatively simple: Ranges of the write/read currents and bit resistance values are incorporated as parameterized variables, and no semiconductor devices are used within the model.</description><subject>Antiferromagnetic materials</subject><subject>Applied sciences</subject><subject>Circuits</subject><subject>Decoding</subject><subject>Electronics</subject><subject>Endurance</subject><subject>Energy use</subject><subject>Exact sciences and technology</subject><subject>Giant magnetoresistance</subject><subject>High speed</subject><subject>Hysteresis</subject><subject>Magnetic device characterization, design, and modeling</subject><subject>Magnetic devices</subject><subject>Magnetic fields</subject><subject>Magnetic materials</subject><subject>Magnetic separation</subject><subject>Magnetic switching</subject><subject>Magnetism</subject><subject>Material storage</subject><subject>Mathematical models</subject><subject>Semiconductor electronics. Microelectronics. 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Solid state devices</topic><topic>Semiconductor memory</topic><topic>Semiconductors</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>Das, B.</creatorcontrib><creatorcontrib>Black, W.C.</creatorcontrib><creatorcontrib>Pohm, A.V.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on magnetics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Das, B.</au><au>Black, W.C.</au><au>Pohm, A.V.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Universal HSPICE macromodel for giant magnetoresistance memory bits</atitle><jtitle>IEEE transactions on magnetics</jtitle><stitle>TMAG</stitle><date>2000-07-01</date><risdate>2000</risdate><volume>36</volume><issue>4</issue><spage>2062</spage><epage>2072</epage><pages>2062-2072</pages><issn>0018-9464</issn><eissn>1941-0069</eissn><coden>IEMGAQ</coden><abstract>Nonvolatile semiconductor storage using giant magnetoresistance (GMR) memory bits has the potential for revolutionizing both high-density and high-speed memory applications with devices exhibiting unlimited write endurance and very low write energy. This paper presents the first universal circuit macromodel for GMR memory bits. The macromodel is realized as a four-terminal subcircuit that emulates GMR bit behavior over a wide range of sense and word-line currents. It realistically models the nonlinear and hysteretic behavior of GMR memory bits, their transient thermal behavior, and the sense-current dependency of their write thresholds. The model is flexible and relatively simple: Ranges of the write/read currents and bit resistance values are incorporated as parameterized variables, and no semiconductor devices are used within the model.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/20.875339</doi><tpages>11</tpages></addata></record> |
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subjects | Antiferromagnetic materials Applied sciences Circuits Decoding Electronics Endurance Energy use Exact sciences and technology Giant magnetoresistance High speed Hysteresis Magnetic device characterization, design, and modeling Magnetic devices Magnetic fields Magnetic materials Magnetic separation Magnetic switching Magnetism Material storage Mathematical models Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductor memory Semiconductors Switches |
title | Universal HSPICE macromodel for giant magnetoresistance memory bits |
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