An experimental 1-Mbit CMOS SRAM with configurable organization and operation

A 1-Mb SRAM (static random-access memory) configurable as a 128-kb*8, 256-kb*4, or 1-Mb*1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1988-10, Vol.23 (5), p.1085-1094
Hauptverfasser:	Williams, T., Beilstein, K., El-Kareh, B., Flaker, R., Gravenites, G., Lipa, R., Lee, H.-S., Maslack, J., Pessetto, J., Pokorny, W.F., Roberge, M., Zeller, H.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Buffer storage Cache storage Circuit testing CMOS process Decoding Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Military computing Packaging Random access memory Semiconductor device measurement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solid state circuits
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