An experimental 1-Mbit CMOS SRAM with configurable organization and operation
A 1-Mb SRAM (static random-access memory) configurable as a 128-kb*8, 256-kb*4, or 1-Mb*1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1988-10, Vol.23 (5), p.1085-1094 |
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| container_end_page | 1094 |
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| container_issue | 5 |
| container_start_page | 1085 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 23 |
| creator | Williams, T. Beilstein, K. El-Kareh, B. Flaker, R. Gravenites, G. Lipa, R. Lee, H.-S. Maslack, J. Pessetto, J. Pokorny, W.F. Roberge, M. Zeller, H. |
| description | A 1-Mb SRAM (static random-access memory) configurable as a 128-kb*8, 256-kb*4, or 1-Mb*1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7- mu m geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 mu m/sup 2/.< > |
| doi_str_mv | 10.1109/4.5929 |
| format | Article |
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It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7- mu m geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 mu m/sup 2/.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.5929</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Buffer storage ; Cache storage ; Circuit testing ; CMOS process ; Decoding ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Military computing ; Packaging ; Random access memory ; Semiconductor device measurement ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Solid state circuits</subject><ispartof>IEEE journal of solid-state circuits, 1988-10, Vol.23 (5), p.1085-1094</ispartof><rights>1990 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c298t-55e606850f2de7abb8ec3b4360b867789ed31bb018b8217ea9a6dccbbd863dd23</citedby><cites>FETCH-LOGICAL-c298t-55e606850f2de7abb8ec3b4360b867789ed31bb018b8217ea9a6dccbbd863dd23</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5929$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5929$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=6914848$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Williams, T.</creatorcontrib><creatorcontrib>Beilstein, K.</creatorcontrib><creatorcontrib>El-Kareh, B.</creatorcontrib><creatorcontrib>Flaker, R.</creatorcontrib><creatorcontrib>Gravenites, G.</creatorcontrib><creatorcontrib>Lipa, R.</creatorcontrib><creatorcontrib>Lee, H.-S.</creatorcontrib><creatorcontrib>Maslack, J.</creatorcontrib><creatorcontrib>Pessetto, J.</creatorcontrib><creatorcontrib>Pokorny, W.F.</creatorcontrib><creatorcontrib>Roberge, M.</creatorcontrib><creatorcontrib>Zeller, H.</creatorcontrib><title>An experimental 1-Mbit CMOS SRAM with configurable organization and operation</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A 1-Mb SRAM (static random-access memory) configurable as a 128-kb*8, 256-kb*4, or 1-Mb*1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7- mu m geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 mu m/sup 2/.< ></description><subject>Applied sciences</subject><subject>Buffer storage</subject><subject>Cache storage</subject><subject>Circuit testing</subject><subject>CMOS process</subject><subject>Decoding</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Military computing</subject><subject>Packaging</subject><subject>Random access memory</subject><subject>Semiconductor device measurement</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Solid state circuits</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1988</creationdate><recordtype>article</recordtype><recordid>eNpFkMtLAzEQh4MoWKuePeYg3rYmu9lscizFF3QpWAVvS5KdrZFtUpMtPv56tw_qafgx33zMDEKXlIwoJfKWjXKZyiM0oHkuElpkb8doQAgViUwJOUVnMX70kTFBB6gcOwzfKwh2Ca5TLaZJqW2HJ-VsjufP4xJ_2e4dG-8au1gHpVvAPiyUs7-qs95h5Wrs-_ltOkcnjWojXOzrEL3e371MHpPp7OFpMp4mJpWiS_IcOOEiJ01aQ6G0FmAyzTJOtOBFISTUGdW6X1mLlBagpOK1MVrXgmd1nWZDdLPzroL_XEPsqqWNBtpWOfDrWKWCSVJI8Q-a4GMM0FSr_lIVfipKqs23KlZtvtWD13ujika1TVDO2HiguaRMsI3vaodZADh0t4Y_vBhweg</recordid><startdate>19881001</startdate><enddate>19881001</enddate><creator>Williams, T.</creator><creator>Beilstein, K.</creator><creator>El-Kareh, B.</creator><creator>Flaker, R.</creator><creator>Gravenites, G.</creator><creator>Lipa, R.</creator><creator>Lee, H.-S.</creator><creator>Maslack, J.</creator><creator>Pessetto, J.</creator><creator>Pokorny, W.F.</creator><creator>Roberge, M.</creator><creator>Zeller, H.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19881001</creationdate><title>An experimental 1-Mbit CMOS SRAM with configurable organization and operation</title><author>Williams, T. ; Beilstein, K. ; El-Kareh, B. ; Flaker, R. ; Gravenites, G. ; Lipa, R. ; Lee, H.-S. ; Maslack, J. ; Pessetto, J. ; Pokorny, W.F. ; Roberge, M. ; Zeller, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c298t-55e606850f2de7abb8ec3b4360b867789ed31bb018b8217ea9a6dccbbd863dd23</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1988</creationdate><topic>Applied sciences</topic><topic>Buffer storage</topic><topic>Cache storage</topic><topic>Circuit testing</topic><topic>CMOS process</topic><topic>Decoding</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Military computing</topic><topic>Packaging</topic><topic>Random access memory</topic><topic>Semiconductor device measurement</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Solid state circuits</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Williams, T.</creatorcontrib><creatorcontrib>Beilstein, K.</creatorcontrib><creatorcontrib>El-Kareh, B.</creatorcontrib><creatorcontrib>Flaker, R.</creatorcontrib><creatorcontrib>Gravenites, G.</creatorcontrib><creatorcontrib>Lipa, R.</creatorcontrib><creatorcontrib>Lee, H.-S.</creatorcontrib><creatorcontrib>Maslack, J.</creatorcontrib><creatorcontrib>Pessetto, J.</creatorcontrib><creatorcontrib>Pokorny, W.F.</creatorcontrib><creatorcontrib>Roberge, M.</creatorcontrib><creatorcontrib>Zeller, H.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Williams, T.</au><au>Beilstein, K.</au><au>El-Kareh, B.</au><au>Flaker, R.</au><au>Gravenites, G.</au><au>Lipa, R.</au><au>Lee, H.-S.</au><au>Maslack, J.</au><au>Pessetto, J.</au><au>Pokorny, W.F.</au><au>Roberge, M.</au><au>Zeller, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An experimental 1-Mbit CMOS SRAM with configurable organization and operation</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1988-10-01</date><risdate>1988</risdate><volume>23</volume><issue>5</issue><spage>1085</spage><epage>1094</epage><pages>1085-1094</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 1-Mb SRAM (static random-access memory) configurable as a 128-kb*8, 256-kb*4, or 1-Mb*1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7- mu m geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 mu m/sup 2/.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.5929</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1988-10, Vol.23 (5), p.1085-1094 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_pascalfrancis_primary_6914848 |
| source | IEEE Xplore |
| subjects | Applied sciences Buffer storage Cache storage Circuit testing CMOS process Decoding Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Military computing Packaging Random access memory Semiconductor device measurement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solid state circuits |
| title | An experimental 1-Mbit CMOS SRAM with configurable organization and operation |
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