A gracefully degradable VLSI system for linear programming
The use of a fault-tolerant VLSI system for storing and solving linear programming problems is presented. The system can bear multiple faults in processing elements and/or links and still function with an acceptable performance degradation. It is based on an interconnection pattern consisting of a c...
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| Veröffentlicht in: | IEEE transactions on computers 1989-06, Vol.38 (6), p.853-861 |
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| container_end_page | 861 |
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| container_issue | 6 |
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| container_title | IEEE transactions on computers |
| container_volume | 38 |
| creator | Bertossi, A.A. Bonuccelli, M.A. |
| description | The use of a fault-tolerant VLSI system for storing and solving linear programming problems is presented. The system can bear multiple faults in processing elements and/or links and still function with an acceptable performance degradation. It is based on an interconnection pattern consisting of a complete binary tree in which spare links between cousin nodes are added so as to reconfigure it as a ternary tree. At any given time of a computation, faulty processing elements and/or links are circumvented by using such spare links. It is shown that the total silicon area required by this structure is only a constant factor higher than that of a complete binary tree. The result is used to give an efficient implementation of the simplex algorithm in which the time required to perform a single pivot step matches a previously established lower bound for tree machines in spite of faults.< > |
| doi_str_mv | 10.1109/12.24294 |
| format | Article |
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The system can bear multiple faults in processing elements and/or links and still function with an acceptable performance degradation. It is based on an interconnection pattern consisting of a complete binary tree in which spare links between cousin nodes are added so as to reconfigure it as a ternary tree. At any given time of a computation, faulty processing elements and/or links are circumvented by using such spare links. It is shown that the total silicon area required by this structure is only a constant factor higher than that of a complete binary tree. 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The system can bear multiple faults in processing elements and/or links and still function with an acceptable performance degradation. It is based on an interconnection pattern consisting of a complete binary tree in which spare links between cousin nodes are added so as to reconfigure it as a ternary tree. At any given time of a computation, faulty processing elements and/or links are circumvented by using such spare links. It is shown that the total silicon area required by this structure is only a constant factor higher than that of a complete binary tree. The result is used to give an efficient implementation of the simplex algorithm in which the time required to perform a single pivot step matches a previously established lower bound for tree machines in spite of faults.< ></description><subject>Applied sciences</subject><subject>Binary trees</subject><subject>Costs</subject><subject>Degradation</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Fault tolerance</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Linear programming</subject><subject>Production</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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| ispartof | IEEE transactions on computers, 1989-06, Vol.38 (6), p.853-861 |
| issn | 0018-9340 1557-9956 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_6615327 |
| source | IEEE Xplore |
| subjects | Applied sciences Binary trees Costs Degradation Electronics Exact sciences and technology Fault tolerance Integrated circuits Integrated circuits by function (including memories and processors) Linear programming Production Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Systolic arrays Vectors Very large scale integration |
| title | A gracefully degradable VLSI system for linear programming |
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