Parallel random number generation for VLSI systems using cellular automata
A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binar...
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| Veröffentlicht in: | IEEE transactions on computers 1989-10, Vol.38 (10), p.1466-1473 |
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| container_end_page | 1473 |
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| container_issue | 10 |
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| container_title | IEEE transactions on computers |
| container_volume | 38 |
| creator | Hortensius, P.D. McLeod, R.D. Card, H.C. |
| description | A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each clock cycle and pass standard empirical random number tests. Applications have been demonstrated in the design and analysis of special-purpose accelerators for Monte Carlo simulation of large intractable systems. In addition, significant advantages in pseudorandom built-in self-test of VLSI circuits using cellular automata based RNGs have been demonstrated.< > |
| doi_str_mv | 10.1109/12.35843 |
| format | Article |
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It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each clock cycle and pass standard empirical random number tests. Applications have been demonstrated in the design and analysis of special-purpose accelerators for Monte Carlo simulation of large intractable systems. In addition, significant advantages in pseudorandom built-in self-test of VLSI circuits using cellular automata based RNGs have been demonstrated.< ></description><subject>Application software</subject><subject>Automata</subject><subject>Automatic testing</subject><subject>Circuit testing</subject><subject>Clocks</subject><subject>Exact sciences and technology</subject><subject>Mathematics</subject><subject>Nearest neighbor searches</subject><subject>Numerical analysis</subject><subject>Numerical analysis. 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Scientific computation</topic><topic>Numerical simulation</topic><topic>Parallel processing</topic><topic>Random number generation</topic><topic>Random sequences</topic><topic>Sciences and techniques of general use</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hortensius, P.D.</creatorcontrib><creatorcontrib>McLeod, R.D.</creatorcontrib><creatorcontrib>Card, H.C.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hortensius, P.D.</au><au>McLeod, R.D.</au><au>Card, H.C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Parallel random number generation for VLSI systems using cellular automata</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>1989-10-01</date><risdate>1989</risdate><volume>38</volume><issue>10</issue><spage>1466</spage><epage>1473</epage><pages>1466-1473</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each clock cycle and pass standard empirical random number tests. Applications have been demonstrated in the design and analysis of special-purpose accelerators for Monte Carlo simulation of large intractable systems. In addition, significant advantages in pseudorandom built-in self-test of VLSI circuits using cellular automata based RNGs have been demonstrated.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/12.35843</doi><tpages>8</tpages></addata></record> |
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| identifier | ISSN: 0018-9340 |
| ispartof | IEEE transactions on computers, 1989-10, Vol.38 (10), p.1466-1473 |
| issn | 0018-9340 1557-9956 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Application software Automata Automatic testing Circuit testing Clocks Exact sciences and technology Mathematics Nearest neighbor searches Numerical analysis Numerical analysis. Scientific computation Numerical simulation Parallel processing Random number generation Random sequences Sciences and techniques of general use Very large scale integration |
| title | Parallel random number generation for VLSI systems using cellular automata |
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