A high-performance 0.25- mu m CMOS technology. II. Technology

For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain (S/D) are doped simultaneousl...

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Veröffentlicht in:	IEEE transactions on electron devices 1992-04, Vol.39 (4), p.967-975
Hauptverfasser:	Davari, B., Chang, W.H., Petrillo, K.E., Wong, C.Y., Moy, D., Taur, Y., Wordeman, M.R., Sun, J.Y.-C., Hsu, C.C.-H., Polcari, M.R.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Boron CMOS process CMOS technology Delay Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Implants Integrated circuits Lithography Resists Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sheet materials Surfaces Tungsten
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