Hierarchical yield estimation of large analog integrated circuits

A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation w...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1993-03, Vol.28 (3), p.203-209
Hauptverfasser:	Kurker, C.M., Paulos, J.J., Gyurcsik, R.S., Lu, J.-C.
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog integrated circuits Applied sciences Circuit simulation Circuit testing Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuit yield Integrated circuits Manufacturing processes Monte Carlo methods Performance analysis Predictive models Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solid modeling Yield estimation
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