Hierarchical yield estimation of large analog integrated circuits
A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation w...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1993-03, Vol.28 (3), p.203-209 |
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| container_end_page | 209 |
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| container_issue | 3 |
| container_start_page | 203 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 28 |
| creator | Kurker, C.M. Paulos, J.J. Gyurcsik, R.S. Lu, J.-C. |
| description | A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive.< > |
| doi_str_mv | 10.1109/4.209986 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_pascalfrancis_primary_4697492</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>209986</ieee_id><sourcerecordid>28334078</sourcerecordid><originalsourceid>FETCH-LOGICAL-c304t-f39a583b494d0fd37fbcf9df60d8d561883ea28daf871d57fab70023728c215c3</originalsourceid><addsrcrecordid>eNo9kE1LAzEQhoMoWKvg2VMOIl625ms3ybEUtULBi4K3MM1HjaS7Ndke-u9d2dLTMMzDw7wvQreUzCgl-knMGNFaNWdoQutaVVTyr3M0IYSqSjNCLtFVKT_DKoSiEzRfRp8h2-9oIeFD9MlhX_q4hT52Le4CTpA3HkMLqdvg2PZ-k6H3DtuY7T725RpdBEjF3xznFH2-PH8sltXq_fVtMV9VlhPRV4FrqBVfCy0cCY7LsLZBu9AQp1zdUKW4B6YcBCWpq2WAtSSEccmUZbS2fIoeRu8ud7_74UezjcX6lKD13b4YpjgXRKoBfBxBm7tSsg9ml4c8-WAoMf8dGWHGjgb0_uiEMuQPGVoby4kXjZZCswG7G7HovT9dj44_T2luJw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28334078</pqid></control><display><type>article</type><title>Hierarchical yield estimation of large analog integrated circuits</title><source>IEEE Electronic Library (IEL)</source><creator>Kurker, C.M. ; Paulos, J.J. ; Gyurcsik, R.S. ; Lu, J.-C.</creator><creatorcontrib>Kurker, C.M. ; Paulos, J.J. ; Gyurcsik, R.S. ; Lu, J.-C.</creatorcontrib><description>A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.209986</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Analog integrated circuits ; Applied sciences ; Circuit simulation ; Circuit testing ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Integrated circuit yield ; Integrated circuits ; Manufacturing processes ; Monte Carlo methods ; Performance analysis ; Predictive models ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Solid modeling ; Yield estimation</subject><ispartof>IEEE journal of solid-state circuits, 1993-03, Vol.28 (3), p.203-209</ispartof><rights>1993 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c304t-f39a583b494d0fd37fbcf9df60d8d561883ea28daf871d57fab70023728c215c3</citedby><cites>FETCH-LOGICAL-c304t-f39a583b494d0fd37fbcf9df60d8d561883ea28daf871d57fab70023728c215c3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/209986$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,792,23909,23910,25118,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/209986$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4697492$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kurker, C.M.</creatorcontrib><creatorcontrib>Paulos, J.J.</creatorcontrib><creatorcontrib>Gyurcsik, R.S.</creatorcontrib><creatorcontrib>Lu, J.-C.</creatorcontrib><title>Hierarchical yield estimation of large analog integrated circuits</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive.< ></description><subject>Analog integrated circuits</subject><subject>Applied sciences</subject><subject>Circuit simulation</subject><subject>Circuit testing</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuit yield</subject><subject>Integrated circuits</subject><subject>Manufacturing processes</subject><subject>Monte Carlo methods</subject><subject>Performance analysis</subject><subject>Predictive models</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Solid modeling</subject><subject>Yield estimation</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNo9kE1LAzEQhoMoWKvg2VMOIl625ms3ybEUtULBi4K3MM1HjaS7Ndke-u9d2dLTMMzDw7wvQreUzCgl-knMGNFaNWdoQutaVVTyr3M0IYSqSjNCLtFVKT_DKoSiEzRfRp8h2-9oIeFD9MlhX_q4hT52Le4CTpA3HkMLqdvg2PZ-k6H3DtuY7T725RpdBEjF3xznFH2-PH8sltXq_fVtMV9VlhPRV4FrqBVfCy0cCY7LsLZBu9AQp1zdUKW4B6YcBCWpq2WAtSSEccmUZbS2fIoeRu8ud7_74UezjcX6lKD13b4YpjgXRKoBfBxBm7tSsg9ml4c8-WAoMf8dGWHGjgb0_uiEMuQPGVoby4kXjZZCswG7G7HovT9dj44_T2luJw</recordid><startdate>19930301</startdate><enddate>19930301</enddate><creator>Kurker, C.M.</creator><creator>Paulos, J.J.</creator><creator>Gyurcsik, R.S.</creator><creator>Lu, J.-C.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19930301</creationdate><title>Hierarchical yield estimation of large analog integrated circuits</title><author>Kurker, C.M. ; Paulos, J.J. ; Gyurcsik, R.S. ; Lu, J.-C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c304t-f39a583b494d0fd37fbcf9df60d8d561883ea28daf871d57fab70023728c215c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Analog integrated circuits</topic><topic>Applied sciences</topic><topic>Circuit simulation</topic><topic>Circuit testing</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuit yield</topic><topic>Integrated circuits</topic><topic>Manufacturing processes</topic><topic>Monte Carlo methods</topic><topic>Performance analysis</topic><topic>Predictive models</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Solid modeling</topic><topic>Yield estimation</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kurker, C.M.</creatorcontrib><creatorcontrib>Paulos, J.J.</creatorcontrib><creatorcontrib>Gyurcsik, R.S.</creatorcontrib><creatorcontrib>Lu, J.-C.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kurker, C.M.</au><au>Paulos, J.J.</au><au>Gyurcsik, R.S.</au><au>Lu, J.-C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Hierarchical yield estimation of large analog integrated circuits</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1993-03-01</date><risdate>1993</risdate><volume>28</volume><issue>3</issue><spage>203</spage><epage>209</epage><pages>203-209</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.209986</doi><tpages>7</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1993-03, Vol.28 (3), p.203-209 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_pascalfrancis_primary_4697492 |
| source | IEEE Electronic Library (IEL) |
| subjects | Analog integrated circuits Applied sciences Circuit simulation Circuit testing Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuit yield Integrated circuits Manufacturing processes Monte Carlo methods Performance analysis Predictive models Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solid modeling Yield estimation |
| title | Hierarchical yield estimation of large analog integrated circuits |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T16%3A48%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Hierarchical%20yield%20estimation%20of%20large%20analog%20integrated%20circuits&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Kurker,%20C.M.&rft.date=1993-03-01&rft.volume=28&rft.issue=3&rft.spage=203&rft.epage=209&rft.pages=203-209&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.209986&rft_dat=%3Cproquest_RIE%3E28334078%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=28334078&rft_id=info:pmid/&rft_ieee_id=209986&rfr_iscdi=true |