An integrated CMOS mixed-mode signal processor for disk drive read channel applications
A read channel processor architecture for Winchester disk drive applications is presented, designed to operate with data rates from 10 to 32 Mbits/sec with (1,7) Run Length Limited (RLL) encoding on a 5 volt 1-/spl mu/m CMOS technology. The processor performs the functions of pulse detection and dat...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 1994-01, Vol.41 (1), p.1-11 |
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| container_title | IEEE transactions on circuits and systems. 2, Analog and digital signal processing |
| container_volume | 41 |
| creator | Beomsup Kim Greco, J.D. Yang, H.C. Wu, W.-C.S. Chowdhury, R.F. |
| description | A read channel processor architecture for Winchester disk drive applications is presented, designed to operate with data rates from 10 to 32 Mbits/sec with (1,7) Run Length Limited (RLL) encoding on a 5 volt 1-/spl mu/m CMOS technology. The processor performs the functions of pulse detection and data separation using integrated CMOS analog amplifiers and filters and a digital phase-locked loop (PLL). It integrates many of the functions previously performed with discrete components and has enhanced programmability to more fully support Zoned Bit Recording (ZBR). This paper presents an architectural overview of the processor with comparisons to existing solutions, detailing the system constraints of the architecture. Unique CMOS circuit designs are presented along with the pipelined architecture of the digital PLL.< > |
| doi_str_mv | 10.1109/82.275667 |
| format | Article |
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The processor performs the functions of pulse detection and data separation using integrated CMOS analog amplifiers and filters and a digital phase-locked loop (PLL). It integrates many of the functions previously performed with discrete components and has enhanced programmability to more fully support Zoned Bit Recording (ZBR). This paper presents an architectural overview of the processor with comparisons to existing solutions, detailing the system constraints of the architecture. Unique CMOS circuit designs are presented along with the pipelined architecture of the digital PLL.< ></description><identifier>ISSN: 1057-7130</identifier><identifier>EISSN: 1558-125X</identifier><identifier>DOI: 10.1109/82.275667</identifier><identifier>CODEN: ICSPE5</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; CMOS process ; CMOS technology ; Digital filters ; Disk drives ; Disk recording ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Phase detection ; Phase locked loops ; Pulse amplifiers ; Semiconductor electronics. Microelectronics. Optoelectronics. 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The processor performs the functions of pulse detection and data separation using integrated CMOS analog amplifiers and filters and a digital phase-locked loop (PLL). It integrates many of the functions previously performed with discrete components and has enhanced programmability to more fully support Zoned Bit Recording (ZBR). This paper presents an architectural overview of the processor with comparisons to existing solutions, detailing the system constraints of the architecture. Unique CMOS circuit designs are presented along with the pipelined architecture of the digital PLL.< ></description><subject>Applied sciences</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Digital filters</subject><subject>Disk drives</subject><subject>Disk recording</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Phase detection</subject><subject>Phase locked loops</subject><subject>Pulse amplifiers</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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The processor performs the functions of pulse detection and data separation using integrated CMOS analog amplifiers and filters and a digital phase-locked loop (PLL). It integrates many of the functions previously performed with discrete components and has enhanced programmability to more fully support Zoned Bit Recording (ZBR). This paper presents an architectural overview of the processor with comparisons to existing solutions, detailing the system constraints of the architecture. Unique CMOS circuit designs are presented along with the pipelined architecture of the digital PLL.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/82.275667</doi><tpages>11</tpages></addata></record> |
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| identifier | ISSN: 1057-7130 |
| ispartof | IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 1994-01, Vol.41 (1), p.1-11 |
| issn | 1057-7130 1558-125X |
| language | eng |
| recordid | cdi_pascalfrancis_primary_3989448 |
| source | IEEE/IET Electronic Library |
| subjects | Applied sciences CMOS process CMOS technology Digital filters Disk drives Disk recording Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Phase detection Phase locked loops Pulse amplifiers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal processing Winches |
| title | An integrated CMOS mixed-mode signal processor for disk drive read channel applications |
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