The performance analysis and implementation of an input access scheme in a high-speed packet switch
The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input port maintains a separate queue for each of the outputs, thus n/sup 2/ input queues in an (n/spl times/n) switch. Using synchronous operation, at most one pack...
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| Veröffentlicht in: | IEEE transactions on communications 1994-12, Vol.42 (12), p.3189-3199 |
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| container_title | IEEE transactions on communications |
| container_volume | 42 |
| creator | Mehmet-Ali, M.K. Youssefi, M. Nguyen, H.T. |
| description | The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input port maintains a separate queue for each of the outputs, thus n/sup 2/ input queues in an (n/spl times/n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. We derive lower and upper bounds for the throughput which show close to optimal performance. The bounds are very tight and approach to unity for switch sizes on the order of a hundred under any traffic load, which is a significant result by itself. Then the mean packet delay is derived and its variance is bounded. A neural network implementation of this input access scheme is given. The energy function of the network, its optimized parameters and the connection matrix are determined. Simulation results of the neural network fall between the theoretical throughput bounds.< > |
| doi_str_mv | 10.1109/26.339840 |
| format | Article |
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In this switch, each input port maintains a separate queue for each of the outputs, thus n/sup 2/ input queues in an (n/spl times/n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. We derive lower and upper bounds for the throughput which show close to optimal performance. The bounds are very tight and approach to unity for switch sizes on the order of a hundred under any traffic load, which is a significant result by itself. Then the mean packet delay is derived and its variance is bounded. A neural network implementation of this input access scheme is given. The energy function of the network, its optimized parameters and the connection matrix are determined. Simulation results of the neural network fall between the theoretical throughput bounds.< ></description><identifier>ISSN: 0090-6778</identifier><identifier>EISSN: 1558-0857</identifier><identifier>DOI: 10.1109/26.339840</identifier><identifier>CODEN: IECMBT</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Asynchronous transfer mode ; B-ISDN ; Delay ; Exact sciences and technology ; Fabrics ; Neural networks ; Optical packet switching ; Packet switching ; Performance analysis ; Switches ; Switching and signalling ; Systems, networks and services of telecommunications ; Telecommunications ; Telecommunications and information theory ; Throughput</subject><ispartof>IEEE transactions on communications, 1994-12, Vol.42 (12), p.3189-3199</ispartof><rights>1995 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c306t-a6cecbebf24d0f3a53a574070eea9b4d70050a1a8e82f452dbc61087f1bca7fb3</citedby><cites>FETCH-LOGICAL-c306t-a6cecbebf24d0f3a53a574070eea9b4d70050a1a8e82f452dbc61087f1bca7fb3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/339840$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/339840$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=3379660$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Mehmet-Ali, M.K.</creatorcontrib><creatorcontrib>Youssefi, M.</creatorcontrib><creatorcontrib>Nguyen, H.T.</creatorcontrib><title>The performance analysis and implementation of an input access scheme in a high-speed packet switch</title><title>IEEE transactions on communications</title><addtitle>TCOMM</addtitle><description>The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input port maintains a separate queue for each of the outputs, thus n/sup 2/ input queues in an (n/spl times/n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. We derive lower and upper bounds for the throughput which show close to optimal performance. The bounds are very tight and approach to unity for switch sizes on the order of a hundred under any traffic load, which is a significant result by itself. Then the mean packet delay is derived and its variance is bounded. A neural network implementation of this input access scheme is given. The energy function of the network, its optimized parameters and the connection matrix are determined. Simulation results of the neural network fall between the theoretical throughput bounds.< ></description><subject>Applied sciences</subject><subject>Asynchronous transfer mode</subject><subject>B-ISDN</subject><subject>Delay</subject><subject>Exact sciences and technology</subject><subject>Fabrics</subject><subject>Neural networks</subject><subject>Optical packet switching</subject><subject>Packet switching</subject><subject>Performance analysis</subject><subject>Switches</subject><subject>Switching and signalling</subject><subject>Systems, networks and services of telecommunications</subject><subject>Telecommunications</subject><subject>Telecommunications and information theory</subject><subject>Throughput</subject><issn>0090-6778</issn><issn>1558-0857</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1994</creationdate><recordtype>article</recordtype><recordid>eNpNkL1LxEAQxRdR8DwtbK22EMEiOskmu5tSxC84sNE6TDazZjVfZnKI_7057xBhYIb3fvOKJ8RpDFdxDPl1oq-Uym0Ke2IRZ5mNwGZmXywAcoi0MfZQHDG_A0AKSi2Ee6lJDjT6fmyxcySxw-abA89HJUM7NNRSN-EU-k72flZl6Ib1JNE5Ypbs6hmYNYmyDm91xANRJQd0HzRJ_gqTq4_FgceG6WS3l-L1_u7l9jFaPT883d6sIqdATxFqR66k0idpBV5hNo9JwQAR5mVaGYAMMEZLNvFpllSl0zFY4-PSofGlWoqLbe4w9p9r4qloAztqGuyoX3ORWG2VSvMZvNyCbuyZR_LFMIYWx-8ihmJTY5HoYlvjzJ7vQpEdNn6cWwr896CUybXeYGdbLBDRP_c34wcEdntD</recordid><startdate>19941201</startdate><enddate>19941201</enddate><creator>Mehmet-Ali, M.K.</creator><creator>Youssefi, M.</creator><creator>Nguyen, H.T.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19941201</creationdate><title>The performance analysis and implementation of an input access scheme in a high-speed packet switch</title><author>Mehmet-Ali, M.K. ; Youssefi, M. ; Nguyen, H.T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c306t-a6cecbebf24d0f3a53a574070eea9b4d70050a1a8e82f452dbc61087f1bca7fb3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Applied sciences</topic><topic>Asynchronous transfer mode</topic><topic>B-ISDN</topic><topic>Delay</topic><topic>Exact sciences and technology</topic><topic>Fabrics</topic><topic>Neural networks</topic><topic>Optical packet switching</topic><topic>Packet switching</topic><topic>Performance analysis</topic><topic>Switches</topic><topic>Switching and signalling</topic><topic>Systems, networks and services of telecommunications</topic><topic>Telecommunications</topic><topic>Telecommunications and information theory</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mehmet-Ali, M.K.</creatorcontrib><creatorcontrib>Youssefi, M.</creatorcontrib><creatorcontrib>Nguyen, H.T.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on communications</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mehmet-Ali, M.K.</au><au>Youssefi, M.</au><au>Nguyen, H.T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>The performance analysis and implementation of an input access scheme in a high-speed packet switch</atitle><jtitle>IEEE transactions on communications</jtitle><stitle>TCOMM</stitle><date>1994-12-01</date><risdate>1994</risdate><volume>42</volume><issue>12</issue><spage>3189</spage><epage>3199</epage><pages>3189-3199</pages><issn>0090-6778</issn><eissn>1558-0857</eissn><coden>IECMBT</coden><abstract>The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input port maintains a separate queue for each of the outputs, thus n/sup 2/ input queues in an (n/spl times/n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. We derive lower and upper bounds for the throughput which show close to optimal performance. The bounds are very tight and approach to unity for switch sizes on the order of a hundred under any traffic load, which is a significant result by itself. Then the mean packet delay is derived and its variance is bounded. A neural network implementation of this input access scheme is given. The energy function of the network, its optimized parameters and the connection matrix are determined. Simulation results of the neural network fall between the theoretical throughput bounds.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/26.339840</doi><tpages>11</tpages></addata></record> |
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| ispartof | IEEE transactions on communications, 1994-12, Vol.42 (12), p.3189-3199 |
| issn | 0090-6778 1558-0857 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Asynchronous transfer mode B-ISDN Delay Exact sciences and technology Fabrics Neural networks Optical packet switching Packet switching Performance analysis Switches Switching and signalling Systems, networks and services of telecommunications Telecommunications Telecommunications and information theory Throughput |
| title | The performance analysis and implementation of an input access scheme in a high-speed packet switch |
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