A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability
This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2013-12, Vol.48 (12), p.3028-3037 |
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| container_end_page | 3037 |
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| container_issue | 12 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 48 |
| creator | McLachlan, Roddy C. Gillespie, Alan Coln, Michael C. W. Chisholm, Douglas Lee, Denise T. |
| description | This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers. |
| doi_str_mv | 10.1109/JSSC.2013.2278449 |
| format | Article |
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W. ; Chisholm, Douglas ; Lee, Denise T.</creator><creatorcontrib>McLachlan, Roddy C. ; Gillespie, Alan ; Coln, Michael C. W. ; Chisholm, Douglas ; Lee, Denise T.</creatorcontrib><description>This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2013.2278449</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Accuracy ; Applied sciences ; Calibration ; Circuit properties ; Design. Technologies. Operation analysis. Testing ; digital-analog conversion ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; Force ; Integrated circuits ; linearity ; Noise ; Resistance ; Resistors ; Semiconductor electronics. Microelectronics. Optoelectronics. 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(IEEE) Dec 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c238t-8f313c34e830c8af2127f6db25ed74a65d74dc200e5bbbc79edfefdaeb4578db3</citedby><cites>FETCH-LOGICAL-c238t-8f313c34e830c8af2127f6db25ed74a65d74dc200e5bbbc79edfefdaeb4578db3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6587828$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,796,23930,23931,25140,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6587828$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=28073557$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>McLachlan, Roddy C.</creatorcontrib><creatorcontrib>Gillespie, Alan</creatorcontrib><creatorcontrib>Coln, Michael C. W.</creatorcontrib><creatorcontrib>Chisholm, Douglas</creatorcontrib><creatorcontrib>Lee, Denise T.</creatorcontrib><title>A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.</description><subject>Accuracy</subject><subject>Applied sciences</subject><subject>Calibration</subject><subject>Circuit properties</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>digital-analog conversion</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Force</subject><subject>Integrated circuits</subject><subject>linearity</subject><subject>Noise</subject><subject>Resistance</subject><subject>Resistors</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal convertors</subject><subject>Switches</subject><subject>Switching circuits</subject><subject>Switching, multiplexing, switched capacity circuits</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtOwzAQhi0EEqVwAMTGEmJHUj9jZ1mFR4uqsgivXWQ7jkgJSYjTRTkBZ-AUnIGjcBJctepmRqP5_n9GPwCnGIUYo3h0l6ZJSBCmISFCMhbvgQHmXAZY0Jd9MEAIyyAmCB2CI-cWfmRM4gFIx5AgDZOqMW-VdQ5ejRP4XPavMF3qoG3f4XQ-u4Qi5LB-Gv19fU8-4bwpnYWqziEKEYceGv3-JDDtlS6rsl8dg4NCVc6ebPsQPN5cPySTYHZ_O03Gs8AQKvtAFhRTQ5mVFBmpCoKJKKJcE25zwVTEfc2Nf9lyrbURsc0LW-TKasaFzDUdgvONb9s1H0vr-mzRLLvan8wwixAjDMfUU3hDma5xrrNF1nblu-pWGUbZOrtsnV22zi7bZuc1F1tn5Yyqik7VpnQ7IZFIUM6F5842XGmt3a0jLoUkkv4DKE91Uw</recordid><startdate>201312</startdate><enddate>201312</enddate><creator>McLachlan, Roddy C.</creator><creator>Gillespie, Alan</creator><creator>Coln, Michael C. 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W. ; Chisholm, Douglas ; Lee, Denise T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c238t-8f313c34e830c8af2127f6db25ed74a65d74dc200e5bbbc79edfefdaeb4578db3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Accuracy</topic><topic>Applied sciences</topic><topic>Calibration</topic><topic>Circuit properties</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>digital-analog conversion</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Force</topic><topic>Integrated circuits</topic><topic>linearity</topic><topic>Noise</topic><topic>Resistance</topic><topic>Resistors</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal convertors</topic><topic>Switches</topic><topic>Switching circuits</topic><topic>Switching, multiplexing, switched capacity circuits</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>McLachlan, Roddy C.</creatorcontrib><creatorcontrib>Gillespie, Alan</creatorcontrib><creatorcontrib>Coln, Michael C. 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W.</au><au>Chisholm, Douglas</au><au>Lee, Denise T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2013-12</date><risdate>2013</risdate><volume>48</volume><issue>12</issue><spage>3028</spage><epage>3037</epage><pages>3028-3037</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2013.2278449</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2013-12, Vol.48 (12), p.3028-3037 |
| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Accuracy Applied sciences Calibration Circuit properties Design. Technologies. Operation analysis. Testing digital-analog conversion Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Force Integrated circuits linearity Noise Resistance Resistors Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Switches Switching circuits Switching, multiplexing, switched capacity circuits |
| title | A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability |
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