16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder

In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2 ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-...

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Veröffentlicht in:	IEEE transactions on applied superconductivity 2013-06, Vol.23 (3), p.1700605-1700605
Hauptverfasser:	Dorojevets, M., Ayala, C. L., Yoshikawa, N., Fujimaki, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Applied sciences Bias Chip formation Circuit properties Clocks Design. Technologies. Operation analysis. Testing digital arithmetic Digital circuits Educational institutions Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics Error analysis Exact sciences and technology Flux Generators Integrated circuits Integrated circuits by function (including memories and processors) Logic gates Low frequencies Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors superconducting integrated circuits superconducting logic circuits Superconductivity Testing Voltage
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