16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder
In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2 ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-...
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| Veröffentlicht in: | IEEE transactions on applied superconductivity 2013-06, Vol.23 (3), p.1700605-1700605 |
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| container_title | IEEE transactions on applied superconductivity |
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| creator | Dorojevets, M. Ayala, C. L. Yoshikawa, N. Fujimaki, A. |
| description | In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2 ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm 2 . It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8%/-10.7%. |
| doi_str_mv | 10.1109/TASC.2012.2233846 |
| format | Article |
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L.</creatorcontrib><creatorcontrib>Yoshikawa, N.</creatorcontrib><creatorcontrib>Fujimaki, A.</creatorcontrib><title>16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder</title><title>IEEE transactions on applied superconductivity</title><addtitle>TASC</addtitle><description>In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2 ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm 2 . It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8%/-10.7%.</description><subject>Adders</subject><subject>Applied sciences</subject><subject>Bias</subject><subject>Chip formation</subject><subject>Circuit properties</subject><subject>Clocks</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>digital arithmetic</subject><subject>Digital circuits</subject><subject>Educational institutions</subject><subject>Electric potential</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Error analysis</subject><subject>Exact sciences and technology</subject><subject>Flux</subject><subject>Generators</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Logic gates</subject><subject>Low frequencies</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal convertors</subject><subject>superconducting integrated circuits</subject><subject>superconducting logic circuits</subject><subject>Superconductivity</subject><subject>Testing</subject><subject>Voltage</subject><issn>1051-8223</issn><issn>1558-2515</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLw0AUhQdRsFZ_gLgJiODC1HvnkUmWtVgVCj5acTlMJjeQkiZ1phX89ya0dOHqXjjfORwOY5cII0TI7hfj-WTEAfmIcyFSmRyxASqVxlyhOu5-UBinnXbKzkJYAqBMpRqwO0zih2oTfdkfit-qNdVVQ0U0X1sfKF54ouhjPn2PxkVB_pydlLYOdLG_Q_Y5fVxMnuPZ69PLZDyLnVDJJubOcSRIRSlKDQQiAxCgIQeNBWVWEWiJWubEC6lK5SAFnUGSJNIWeZ6IIbvd5a59-72lsDGrKjiqa9tQuw0GhcykEAJVh17_Q5ft1jddO4Nc8y5Tq7SjcEc534bgqTRrX62s_zUIpt_P9PuZfj-z36_z3OyTbXC2Lr1tXBUORq4VzzLZN7jacRURHeREpKAkiD_zdHPD</recordid><startdate>20130601</startdate><enddate>20130601</enddate><creator>Dorojevets, M.</creator><creator>Ayala, C. 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L.</au><au>Yoshikawa, N.</au><au>Fujimaki, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder</atitle><jtitle>IEEE transactions on applied superconductivity</jtitle><stitle>TASC</stitle><date>2013-06-01</date><risdate>2013</risdate><volume>23</volume><issue>3</issue><spage>1700605</spage><epage>1700605</epage><pages>1700605-1700605</pages><issn>1051-8223</issn><eissn>1558-2515</eissn><coden>ITASE9</coden><abstract>In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2 ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm 2 . It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8%/-10.7%.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TASC.2012.2233846</doi><tpages>1</tpages></addata></record> |
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| subjects | Adders Applied sciences Bias Chip formation Circuit properties Clocks Design. Technologies. Operation analysis. Testing digital arithmetic Digital circuits Educational institutions Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics Error analysis Exact sciences and technology Flux Generators Integrated circuits Integrated circuits by function (including memories and processors) Logic gates Low frequencies Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors superconducting integrated circuits superconducting logic circuits Superconductivity Testing Voltage |
| title | 16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder |
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