Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation
We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness...
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| Veröffentlicht in: | IEEE electron device letters 2013-06, Vol.34 (6), p.756-758 |
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| container_end_page | 758 |
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| container_issue | 6 |
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| container_title | IEEE electron device letters |
| container_volume | 34 |
| creator | JANG, Ki-Hyun JANG, Hyun-June PARK, Jin-Kwon CHO, Won-Ju |
| description | We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase. The DG mode can obtain a larger memory window, reduced operation voltage, and improved reliability compared with the conventional single-gate mode operation. |
| doi_str_mv | 10.1109/LED.2013.2256770 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_pascalfrancis_primary_27484879</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6513279</ieee_id><sourcerecordid>2979186151</sourcerecordid><originalsourceid>FETCH-LOGICAL-c420t-f33a7a19fed71533f7a66ff8b539c637348e30c85fd6262544c786cf7991289b3</originalsourceid><addsrcrecordid>eNpdkEtLAzEUhYMoWKt7wc2ACG6m5v1Ylr4UK11Y3YY0TeyUtBmTKdJ_75QWF67u4nzncPkAuEWwhxBUT9PRsIchIj2MGRcCnoEOYkyWkHFyDjpQUFQSBPkluMp5DSGiVNAOeH13wZf9TR0qX7llMdyZUExM44rByqQvV8yTqYtxMHlVvLlNTPvCx1RM40_5GUNjWmJWu2SaKm6vwYU3Ibub0-2Cj_FoPngup7PJy6A_LS3FsCk9IUYYpLxbCsQI8cJw7r1cMKIsJ4JQ6Qi0kvklxxwzSq2Q3HqhFMJSLUgXPB536xS_dy43elNl60IwWxd3WSOKhFQEK9yi9__QddylbfudRoQxzLDAsqXgkbIp5pyc13WqNibtNYL6YFe3dvXBrj7ZbSsPp2GTrQk-ma2t8l8PCyqpFKrl7o5c5Zz7izlDBLfpL9s-f4o</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1355252728</pqid></control><display><type>article</type><title>Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation</title><source>IEEE Electronic Library (IEL)</source><creator>JANG, Ki-Hyun ; JANG, Hyun-June ; PARK, Jin-Kwon ; CHO, Won-Ju</creator><creatorcontrib>JANG, Ki-Hyun ; JANG, Hyun-June ; PARK, Jin-Kwon ; CHO, Won-Ju</creatorcontrib><description>We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase. The DG mode can obtain a larger memory window, reduced operation voltage, and improved reliability compared with the conventional single-gate mode operation.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2013.2256770</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Buried oxide (BOX) ; capacitive coupling ; Charge ; charge trap Flash (CTF) ; coupling ratio ; Design. Technologies. Operation analysis. Testing ; Devices ; dual-gate (DG) ; Electric potential ; Electronics ; Exact sciences and technology ; Flash memory (computers) ; Gates ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Joining ; Magnetic and optical mass memories ; Oxides ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; silicon-on-insulator (SOI) ; Storage and reproduction of information ; Voltage</subject><ispartof>IEEE electron device letters, 2013-06, Vol.34 (6), p.756-758</ispartof><rights>2014 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jun 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c420t-f33a7a19fed71533f7a66ff8b539c637348e30c85fd6262544c786cf7991289b3</citedby><cites>FETCH-LOGICAL-c420t-f33a7a19fed71533f7a66ff8b539c637348e30c85fd6262544c786cf7991289b3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6513279$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6513279$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=27484879$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>JANG, Ki-Hyun</creatorcontrib><creatorcontrib>JANG, Hyun-June</creatorcontrib><creatorcontrib>PARK, Jin-Kwon</creatorcontrib><creatorcontrib>CHO, Won-Ju</creatorcontrib><title>Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase. The DG mode can obtain a larger memory window, reduced operation voltage, and improved reliability compared with the conventional single-gate mode operation.</description><subject>Applied sciences</subject><subject>Buried oxide (BOX)</subject><subject>capacitive coupling</subject><subject>Charge</subject><subject>charge trap Flash (CTF)</subject><subject>coupling ratio</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>dual-gate (DG)</subject><subject>Electric potential</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Flash memory (computers)</subject><subject>Gates</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Joining</subject><subject>Magnetic and optical mass memories</subject><subject>Oxides</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>silicon-on-insulator (SOI)</subject><subject>Storage and reproduction of information</subject><subject>Voltage</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLAzEUhYMoWKt7wc2ACG6m5v1Ylr4UK11Y3YY0TeyUtBmTKdJ_75QWF67u4nzncPkAuEWwhxBUT9PRsIchIj2MGRcCnoEOYkyWkHFyDjpQUFQSBPkluMp5DSGiVNAOeH13wZf9TR0qX7llMdyZUExM44rByqQvV8yTqYtxMHlVvLlNTPvCx1RM40_5GUNjWmJWu2SaKm6vwYU3Ibub0-2Cj_FoPngup7PJy6A_LS3FsCk9IUYYpLxbCsQI8cJw7r1cMKIsJ4JQ6Qi0kvklxxwzSq2Q3HqhFMJSLUgXPB536xS_dy43elNl60IwWxd3WSOKhFQEK9yi9__QddylbfudRoQxzLDAsqXgkbIp5pyc13WqNibtNYL6YFe3dvXBrj7ZbSsPp2GTrQk-ma2t8l8PCyqpFKrl7o5c5Zz7izlDBLfpL9s-f4o</recordid><startdate>20130601</startdate><enddate>20130601</enddate><creator>JANG, Ki-Hyun</creator><creator>JANG, Hyun-June</creator><creator>PARK, Jin-Kwon</creator><creator>CHO, Won-Ju</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20130601</creationdate><title>Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation</title><author>JANG, Ki-Hyun ; JANG, Hyun-June ; PARK, Jin-Kwon ; CHO, Won-Ju</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c420t-f33a7a19fed71533f7a66ff8b539c637348e30c85fd6262544c786cf7991289b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Applied sciences</topic><topic>Buried oxide (BOX)</topic><topic>capacitive coupling</topic><topic>Charge</topic><topic>charge trap Flash (CTF)</topic><topic>coupling ratio</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>dual-gate (DG)</topic><topic>Electric potential</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Flash memory (computers)</topic><topic>Gates</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Joining</topic><topic>Magnetic and optical mass memories</topic><topic>Oxides</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>silicon-on-insulator (SOI)</topic><topic>Storage and reproduction of information</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>JANG, Ki-Hyun</creatorcontrib><creatorcontrib>JANG, Hyun-June</creatorcontrib><creatorcontrib>PARK, Jin-Kwon</creatorcontrib><creatorcontrib>CHO, Won-Ju</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JANG, Ki-Hyun</au><au>JANG, Hyun-June</au><au>PARK, Jin-Kwon</au><au>CHO, Won-Ju</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2013-06-01</date><risdate>2013</risdate><volume>34</volume><issue>6</issue><spage>756</spage><epage>758</epage><pages>756-758</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase. The DG mode can obtain a larger memory window, reduced operation voltage, and improved reliability compared with the conventional single-gate mode operation.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2013.2256770</doi><tpages>3</tpages></addata></record> |
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| ispartof | IEEE electron device letters, 2013-06, Vol.34 (6), p.756-758 |
| issn | 0741-3106 1558-0563 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Buried oxide (BOX) capacitive coupling Charge charge trap Flash (CTF) coupling ratio Design. Technologies. Operation analysis. Testing Devices dual-gate (DG) Electric potential Electronics Exact sciences and technology Flash memory (computers) Gates Integrated circuits Integrated circuits by function (including memories and processors) Joining Magnetic and optical mass memories Oxides Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices silicon-on-insulator (SOI) Storage and reproduction of information Voltage |
| title | Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T19%3A21%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Self-Amplified%20Dual%20Gate%20Charge%20Trap%20Flash%20Memory%20for%20Low-Voltage%20Operation&rft.jtitle=IEEE%20electron%20device%20letters&rft.au=JANG,%20Ki-Hyun&rft.date=2013-06-01&rft.volume=34&rft.issue=6&rft.spage=756&rft.epage=758&rft.pages=756-758&rft.issn=0741-3106&rft.eissn=1558-0563&rft.coden=EDLEDZ&rft_id=info:doi/10.1109/LED.2013.2256770&rft_dat=%3Cproquest_RIE%3E2979186151%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1355252728&rft_id=info:pmid/&rft_ieee_id=6513279&rfr_iscdi=true |