A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories

This paper presents a built-in self repair analyzer with the optimal repair rate for memory arrays with redundancy. The proposed method requires only a single test, even in the worst case. By performing the must-repair analysis on the fly during the test, it selectively stores fault addresses, and t...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2013-02, Vol.21 (2), p.281-291
Hauptverfasser:	Jaeyong Chung, Joonsung Park, Abraham, J. A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Built-in self repair (BISR) Built-in self-test Circuit faults Circuit properties Computer aided manufacturing Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories Maintenance engineering memory test redundancy allocation Registers repair analysis Resource management Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices spare allocation Storage and reproduction of information System-on-a-chip
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