A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction
In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With th...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2013-02, Vol.21 (2), p.270-280 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | CHEN, You-Gang TSAO, Hen-Wai HWANG, Chorng-Sii |
| description | In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-μm technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption. |
| doi_str_mv | 10.1109/TVLSI.2011.2182216 |
| format | Article |
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A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-μm technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. 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A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-μm technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption.</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>Clocks</subject><subject>Delay</subject><subject>Delay lines</subject><subject>Delay-locked loop (DLL)</subject><subject>duty-cycle correction (DCC)</subject><subject>edge combiner</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware design languages</subject><subject>Logic gates</subject><subject>Oscillators</subject><subject>Signal convertors</subject><subject>time-to-digital converter (TDC)</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMFOAjEQhhujiYi-gF724nFxOu222yMuoiSbeBD1uClDFysrkHaJ4e1dhDCXmeSf7z98jN1yGHAO5mH6Ub5NBgicD5DniFydsR7PMp2abs67G5RIc-Rwya5i_AbgUhrosWKYjG1s03JNS79aJMOmSUd-4VvbJCMXl-43edzWtQvJp2-_ktG23aXFjhqXFOsQHLV-vbpmF7Vtors57j57Hz9Ni5e0fH2eFMMyJTS6TameoUSYgUBCEkoCyZnmkiSRAZsrUBryOarMkFNZhsbIHOe5yjSS0Vr0GR56KaxjDK6uNsH_2LCrOFR7DdW_hmqvoTpq6KD7A7SxkWxTB7siH08kasiMUPvyu8Ofd86dYtVp0kKIP4R-Y9g</recordid><startdate>20130201</startdate><enddate>20130201</enddate><creator>CHEN, You-Gang</creator><creator>TSAO, Hen-Wai</creator><creator>HWANG, Chorng-Sii</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20130201</creationdate><title>A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction</title><author>CHEN, You-Gang ; TSAO, Hen-Wai ; HWANG, Chorng-Sii</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c297t-cfb2420b032c2c3640c4b714c4cc90a8606708d2659ce655299482d86572c9773</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Circuits of signal characteristics conditioning (including delay circuits)</topic><topic>Clocks</topic><topic>Delay</topic><topic>Delay lines</topic><topic>Delay-locked loop (DLL)</topic><topic>duty-cycle correction (DCC)</topic><topic>edge combiner</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hardware design languages</topic><topic>Logic gates</topic><topic>Oscillators</topic><topic>Signal convertors</topic><topic>time-to-digital converter (TDC)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>CHEN, You-Gang</creatorcontrib><creatorcontrib>TSAO, Hen-Wai</creatorcontrib><creatorcontrib>HWANG, Chorng-Sii</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN, You-Gang</au><au>TSAO, Hen-Wai</au><au>HWANG, Chorng-Sii</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2013-02-01</date><risdate>2013</risdate><volume>21</volume><issue>2</issue><spage>270</spage><epage>280</epage><pages>270-280</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-μm technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2011.2182216</doi><tpages>11</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit properties Circuits of signal characteristics conditioning (including delay circuits) Clocks Delay Delay lines Delay-locked loop (DLL) duty-cycle correction (DCC) edge combiner Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Hardware design languages Logic gates Oscillators Signal convertors time-to-digital converter (TDC) |
| title | A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction |
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