ZeROA: Zero Clock Skew Rotary Oscillatory Array
Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2012-08, Vol.20 (8), p.1528-1532 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Honkote, V. Taskin, B. |
| description | Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal ±1.5% change in the tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1-R5 and ISPD 2010 benchmark circuits. |
| doi_str_mv | 10.1109/TVLSI.2011.2158458 |
| format | Article |
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It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal ±1.5% change in the tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1-R5 and ISPD 2010 benchmark circuits.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2011.2158458</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Arrays ; Benchmark testing ; Circuit properties ; Circuits ; Clocks ; Design automation ; Design engineering ; design methodology ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; High frequencies ; oscillators ; Oscillators, resonators, synthetizers ; Phases ; Registers ; sequential circuits ; Synchronization ; Very large scale integration ; Wires</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2012-08, Vol.20 (8), p.1528-1532</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Aug 2012</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c358t-6b73bfc7e520b35ee532467ecf0424360bb11cbc30a200459083f50f8d7b9af73</citedby><cites>FETCH-LOGICAL-c358t-6b73bfc7e520b35ee532467ecf0424360bb11cbc30a200459083f50f8d7b9af73</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5936660$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5936660$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=26201839$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Honkote, V.</creatorcontrib><creatorcontrib>Taskin, B.</creatorcontrib><title>ZeROA: Zero Clock Skew Rotary Oscillatory Array</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal ±1.5% change in the tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1-R5 and ISPD 2010 benchmark circuits.</description><subject>Applied sciences</subject><subject>Arrays</subject><subject>Benchmark testing</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Design automation</subject><subject>Design engineering</subject><subject>design methodology</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>High frequencies</subject><subject>oscillators</subject><subject>Oscillators, resonators, synthetizers</subject><subject>Phases</subject><subject>Registers</subject><subject>sequential circuits</subject><subject>Synchronization</subject><subject>Very large scale integration</subject><subject>Wires</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE1LAzEQhoMoWKt_QC8LInjZdvK5WW-l-FEoFNrqoZeQjQlsu2002SL996a29OBcZmCed3jnRegWQw9jKPvzj_Fs1COAcY9gLhmXZ6iDOS_yMtV5mkHQXBIMl-gqxiUAZqyEDuov7HQyeMoWNvhs2HizymYr-5NNfavDLptEUzeNbn2aByHo3TW6cLqJ9ubYu-j95Xk-fMvHk9fRcDDODeWyzUVV0MqZwnICFeXWckqYKKxxwAijAqoKY1MZCpoAMF6CpI6Dk59FVWpX0C56PNz9Cv57a2Or1nU0NnnZWL-NCgOVNCkxS-j9P3Tpt2GT3CWKYMKBAEkUOVAm-BiDdeor1Ov0Y4LUPkP1l6HaZ6iOGSbRw_G0jkY3LuiNqeNJSUSiJS0Td3fgamvtac1LKoQA-gt_BXcU</recordid><startdate>20120801</startdate><enddate>20120801</enddate><creator>Honkote, V.</creator><creator>Taskin, B.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20120801</creationdate><title>ZeROA: Zero Clock Skew Rotary Oscillatory Array</title><author>Honkote, V. ; Taskin, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c358t-6b73bfc7e520b35ee532467ecf0424360bb11cbc30a200459083f50f8d7b9af73</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Applied sciences</topic><topic>Arrays</topic><topic>Benchmark testing</topic><topic>Circuit properties</topic><topic>Circuits</topic><topic>Clocks</topic><topic>Design automation</topic><topic>Design engineering</topic><topic>design methodology</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>High frequencies</topic><topic>oscillators</topic><topic>Oscillators, resonators, synthetizers</topic><topic>Phases</topic><topic>Registers</topic><topic>sequential circuits</topic><topic>Synchronization</topic><topic>Very large scale integration</topic><topic>Wires</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Honkote, V.</creatorcontrib><creatorcontrib>Taskin, B.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Honkote, V.</au><au>Taskin, B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>ZeROA: Zero Clock Skew Rotary Oscillatory Array</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2012-08-01</date><risdate>2012</risdate><volume>20</volume><issue>8</issue><spage>1528</spage><epage>1532</epage><pages>1528-1532</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal ±1.5% change in the tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1-R5 and ISPD 2010 benchmark circuits.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2011.2158458</doi><tpages>5</tpages></addata></record> |
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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2012-08, Vol.20 (8), p.1528-1532 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Arrays Benchmark testing Circuit properties Circuits Clocks Design automation Design engineering design methodology Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology High frequencies oscillators Oscillators, resonators, synthetizers Phases Registers sequential circuits Synchronization Very large scale integration Wires |
| title | ZeROA: Zero Clock Skew Rotary Oscillatory Array |
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