Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors

We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power...

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Veröffentlicht in:IEEE journal of solid-state circuits 2012-03, Vol.47 (3), p.769-780
Hauptverfasser: Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Chang, J. S.
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container_title IEEE journal of solid-state circuits
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creator Kwen-Siong Chong
Kok-Leong Chang
Bah-Hwee Gwee
Chang, J. S.
description We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal V DD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery ( V DD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at V DD = 1.2 V, it dissipates 186 μW.
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S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2012-03-01</date><risdate>2012</risdate><volume>47</volume><issue>3</issue><spage>769</spage><epage>780</epage><pages>769-780</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. 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subjects Acoustic signal detection
Applied sciences
Asynchronous-logic
Batteries
Circuit properties
Clocks
Design. Technologies. Operation analysis. Testing
Digital circuits
dynamic voltage scaling
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
GALS
Integrated circuits
Integrated circuits by function (including memories and processors)
Protocols
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Synchronization
synchronous-logic low power
System-on-a-chip
title Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors
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