Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors
We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power...
Gespeichert in:
Veröffentlicht in: | IEEE journal of solid-state circuits 2012-03, Vol.47 (3), p.769-780 |
---|---|
Hauptverfasser: | , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 780 |
---|---|
container_issue | 3 |
container_start_page | 769 |
container_title | IEEE journal of solid-state circuits |
container_volume | 47 |
creator | Kwen-Siong Chong Kok-Leong Chang Bah-Hwee Gwee Chang, J. S. |
description | We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal V DD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery ( V DD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at V DD = 1.2 V, it dissipates 186 μW. |
doi_str_mv | 10.1109/JSSC.2011.2181678 |
format | Article |
fullrecord | <record><control><sourceid>pascalfrancis_RIE</sourceid><recordid>TN_cdi_pascalfrancis_primary_25564987</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6151220</ieee_id><sourcerecordid>25564987</sourcerecordid><originalsourceid>FETCH-LOGICAL-c295t-4ce473d0bd658b2b70a5e6cbf4c364ea4aa00a809e23d09ce151663ac1be7d943</originalsourceid><addsrcrecordid>eNpVkEFLxDAQhYMouK7-APHSi6CHrpk0SZNjWXVVCgpV8FbSNF0jtVmS9bD_3qxdFj0Nb-Z9w8xD6BzwDADLm6eqms8IBpgREMBzcYAmwJhIIc_eD9EEYxCpJBgfo5MQPqOkVMAE2Woz6A_vBvcd0tItrU7U0CaL3jWq7zdpEf7N9W_zD5NcLYqyuk4KHcU60rd2adeqTyq7HGJ58U6bEJwPp-ioU30wZ7s6RW_3d6_zh7R8XjzOizLVRLJ1SrWhedbipuVMNKTJsWKG66ajOuPUKKoUxkpgaUh0SW2AAeeZ0tCYvJU0myIY92rvQvCmq1fefim_qQHX26zqbVb1Nqt6l1VkLkdmpUJ8sfNq0DbsQcIYp1Lk0Xcx-qwxZj_m8QRCcPYDUOR0YA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors</title><source>IEEE Electronic Library (IEL)</source><creator>Kwen-Siong Chong ; Kok-Leong Chang ; Bah-Hwee Gwee ; Chang, J. S.</creator><creatorcontrib>Kwen-Siong Chong ; Kok-Leong Chang ; Bah-Hwee Gwee ; Chang, J. S.</creatorcontrib><description>We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal V DD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery ( V DD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at V DD = 1.2 V, it dissipates 186 μW.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2011.2181678</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Acoustic signal detection ; Applied sciences ; Asynchronous-logic ; Batteries ; Circuit properties ; Clocks ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; dynamic voltage scaling ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; GALS ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Protocols ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Synchronization ; synchronous-logic low power ; System-on-a-chip</subject><ispartof>IEEE journal of solid-state circuits, 2012-03, Vol.47 (3), p.769-780</ispartof><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c295t-4ce473d0bd658b2b70a5e6cbf4c364ea4aa00a809e23d09ce151663ac1be7d943</citedby><cites>FETCH-LOGICAL-c295t-4ce473d0bd658b2b70a5e6cbf4c364ea4aa00a809e23d09ce151663ac1be7d943</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6151220$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27929,27930,54763</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6151220$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=25564987$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kwen-Siong Chong</creatorcontrib><creatorcontrib>Kok-Leong Chang</creatorcontrib><creatorcontrib>Bah-Hwee Gwee</creatorcontrib><creatorcontrib>Chang, J. S.</creatorcontrib><title>Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal V DD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery ( V DD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at V DD = 1.2 V, it dissipates 186 μW.</description><subject>Acoustic signal detection</subject><subject>Applied sciences</subject><subject>Asynchronous-logic</subject><subject>Batteries</subject><subject>Circuit properties</subject><subject>Clocks</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>dynamic voltage scaling</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>GALS</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Protocols</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Synchronization</subject><subject>synchronous-logic low power</subject><subject>System-on-a-chip</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpVkEFLxDAQhYMouK7-APHSi6CHrpk0SZNjWXVVCgpV8FbSNF0jtVmS9bD_3qxdFj0Nb-Z9w8xD6BzwDADLm6eqms8IBpgREMBzcYAmwJhIIc_eD9EEYxCpJBgfo5MQPqOkVMAE2Woz6A_vBvcd0tItrU7U0CaL3jWq7zdpEf7N9W_zD5NcLYqyuk4KHcU60rd2adeqTyq7HGJ58U6bEJwPp-ioU30wZ7s6RW_3d6_zh7R8XjzOizLVRLJ1SrWhedbipuVMNKTJsWKG66ajOuPUKKoUxkpgaUh0SW2AAeeZ0tCYvJU0myIY92rvQvCmq1fefim_qQHX26zqbVb1Nqt6l1VkLkdmpUJ8sfNq0DbsQcIYp1Lk0Xcx-qwxZj_m8QRCcPYDUOR0YA</recordid><startdate>20120301</startdate><enddate>20120301</enddate><creator>Kwen-Siong Chong</creator><creator>Kok-Leong Chang</creator><creator>Bah-Hwee Gwee</creator><creator>Chang, J. S.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20120301</creationdate><title>Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors</title><author>Kwen-Siong Chong ; Kok-Leong Chang ; Bah-Hwee Gwee ; Chang, J. S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-4ce473d0bd658b2b70a5e6cbf4c364ea4aa00a809e23d09ce151663ac1be7d943</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Acoustic signal detection</topic><topic>Applied sciences</topic><topic>Asynchronous-logic</topic><topic>Batteries</topic><topic>Circuit properties</topic><topic>Clocks</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>dynamic voltage scaling</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>GALS</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Protocols</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Synchronization</topic><topic>synchronous-logic low power</topic><topic>System-on-a-chip</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kwen-Siong Chong</creatorcontrib><creatorcontrib>Kok-Leong Chang</creatorcontrib><creatorcontrib>Bah-Hwee Gwee</creatorcontrib><creatorcontrib>Chang, J. S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kwen-Siong Chong</au><au>Kok-Leong Chang</au><au>Bah-Hwee Gwee</au><au>Chang, J. S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2012-03-01</date><risdate>2012</risdate><volume>47</volume><issue>3</issue><spage>769</spage><epage>780</epage><pages>769-780</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal V DD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery ( V DD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at V DD = 1.2 V, it dissipates 186 μW.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2011.2181678</doi><tpages>12</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0018-9200 |
ispartof | IEEE journal of solid-state circuits, 2012-03, Vol.47 (3), p.769-780 |
issn | 0018-9200 1558-173X |
language | eng |
recordid | cdi_pascalfrancis_primary_25564987 |
source | IEEE Electronic Library (IEL) |
subjects | Acoustic signal detection Applied sciences Asynchronous-logic Batteries Circuit properties Clocks Design. Technologies. Operation analysis. Testing Digital circuits dynamic voltage scaling Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology GALS Integrated circuits Integrated circuits by function (including memories and processors) Protocols Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Synchronization synchronous-logic low power System-on-a-chip |
title | Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-12T05%3A41%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Synchronous-Logic%20and%20Globally-Asynchronous-Locally-Synchronous%20(GALS)%20Acoustic%20Digital%20Signal%20Processors&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Kwen-Siong%20Chong&rft.date=2012-03-01&rft.volume=47&rft.issue=3&rft.spage=769&rft.epage=780&rft.pages=769-780&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2011.2181678&rft_dat=%3Cpascalfrancis_RIE%3E25564987%3C/pascalfrancis_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6151220&rfr_iscdi=true |