Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology : Electrostatic Discharge Reliability

Bibliographische Detailangaben

Hauptverfasser:	ALVAREZ, David, CHATTY, Kiran, RUSS, Christian, ABOU-KHALIL, Michel J, JUNJUN LI, GAUTHIER, Robert, ESMARK, Kai, HALBACH, Ralph, SEGUIN, Christopher
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Testing, measurement, noise and reliability Transistors
Online-Zugang:	Volltext
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