Improvement of the Sensing Window on a Capacitorless 1T-DRAM of a FinFET-Based Unified RAM
A novel initialization concept is demonstrated to improve the program efficiency of the 1T-DRAM mode of unified random access memory (URAM). The proposed method involves boosting the gate-induced drain leakage current for the generation of excess holes by pretrapping electrons to the nitride layer p...
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| Veröffentlicht in: | IEEE transactions on electron devices 2009-12, Vol.56 (12), p.3228-3231 |
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| container_issue | 12 |
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| container_title | IEEE transactions on electron devices |
| container_volume | 56 |
| creator | CHOI, Sung-Jin HAN, Jin-Woo KIM, Chung-Jin KIM, Sungho CHOI, Yang-Kyu |
| description | A novel initialization concept is demonstrated to improve the program efficiency of the 1T-DRAM mode of unified random access memory (URAM). The proposed method involves boosting the gate-induced drain leakage current for the generation of excess holes by pretrapping electrons to the nitride layer prior to the activation of 1T-DRAM mode. The proposed initialization concept doubles the current sensing window in 1T-DRAM operation. Due to the potential for soft erasing caused by hot-hole injections into electrons that are trapped in the nitride during the P/E cycling of 1T-DRAM, immunity against soft erasing is confirmed through a dc stress measurement as well. |
| doi_str_mv | 10.1109/TED.2009.2033011 |
| format | Article |
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The proposed method involves boosting the gate-induced drain leakage current for the generation of excess holes by pretrapping electrons to the nitride layer prior to the activation of 1T-DRAM mode. The proposed initialization concept doubles the current sensing window in 1T-DRAM operation. Due to the potential for soft erasing caused by hot-hole injections into electrons that are trapped in the nitride during the P/E cycling of 1T-DRAM, immunity against soft erasing is confirmed through a dc stress measurement as well.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2009.2033011</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>1T-DRAM ; Activation ; Applied sciences ; Capacitorless DRAM ; Compound structure devices ; Cycles ; Design. Technologies. Operation analysis. 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The proposed method involves boosting the gate-induced drain leakage current for the generation of excess holes by pretrapping electrons to the nitride layer prior to the activation of 1T-DRAM mode. The proposed initialization concept doubles the current sensing window in 1T-DRAM operation. Due to the potential for soft erasing caused by hot-hole injections into electrons that are trapped in the nitride during the P/E cycling of 1T-DRAM, immunity against soft erasing is confirmed through a dc stress measurement as well.</description><subject>1T-DRAM</subject><subject>Activation</subject><subject>Applied sciences</subject><subject>Capacitorless DRAM</subject><subject>Compound structure devices</subject><subject>Cycles</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Detection</subject><subject>Drains</subject><subject>DRAM chips</subject><subject>Electron traps</subject><subject>Electronics</subject><subject>embedded memory</subject><subject>Exact sciences and technology</subject><subject>gate-induced drain leakage (GIDL)</subject><subject>GIDL program</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Leakage current</subject><subject>Logic gates</subject><subject>Nitrides</subject><subject>Random access memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Sensors</subject><subject>soft erasing</subject><subject>SONOS</subject><subject>SONOS devices</subject><subject>Stress measurement</subject><subject>Transistors</subject><subject>unified random access memory (URAM)</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kctLAzEQxoMoWB93wUsQ1NPWvDabHLXWByiCVgQvYcwmGtlm62ar-N-b0uLBg5cZhvl9k3x8CO1RMqSU6JPJ-HzICNG5cE4oXUMDWpZVoaWQ62hACFWF5opvoq2U3vMohWAD9Hw9nXXtp5u62OPW4_7N4QcXU4iv-CnEuv3CbcSARzADG_q2a1xKmE6K8_vT24UA8EWIF-NJcQbJ1fgxBh9yz9sdtOGhSW531bfRY-ZGV8XN3eX16PSmsPk7fVGDfKk0k7VninFGhRaVqGpwNRBGFbPEcv9iQREhLFhfEw9MEeC6lllV8m10vLybjXzMXerNNCTrmgaia-fJKKmVYCWpMnn0L8kl54wIlsGDP-B7O-9idmFUKTXTSi3eJUvIdm1KnfNm1oUpdN-GErPIxORMzCITs8okSw5XdyFZaHwH0Yb0q2OMSpbdZ25_yQXn3O-65JQrVfEf8lGRbw</recordid><startdate>20091201</startdate><enddate>20091201</enddate><creator>CHOI, Sung-Jin</creator><creator>HAN, Jin-Woo</creator><creator>KIM, Chung-Jin</creator><creator>KIM, Sungho</creator><creator>CHOI, Yang-Kyu</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Testing</topic><topic>Detection</topic><topic>Drains</topic><topic>DRAM chips</topic><topic>Electron traps</topic><topic>Electronics</topic><topic>embedded memory</topic><topic>Exact sciences and technology</topic><topic>gate-induced drain leakage (GIDL)</topic><topic>GIDL program</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Leakage current</topic><topic>Logic gates</topic><topic>Nitrides</topic><topic>Random access memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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The proposed method involves boosting the gate-induced drain leakage current for the generation of excess holes by pretrapping electrons to the nitride layer prior to the activation of 1T-DRAM mode. The proposed initialization concept doubles the current sensing window in 1T-DRAM operation. Due to the potential for soft erasing caused by hot-hole injections into electrons that are trapped in the nitride during the P/E cycling of 1T-DRAM, immunity against soft erasing is confirmed through a dc stress measurement as well.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2009.2033011</doi><tpages>4</tpages></addata></record> |
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| subjects | 1T-DRAM Activation Applied sciences Capacitorless DRAM Compound structure devices Cycles Design. Technologies. Operation analysis. Testing Detection Drains DRAM chips Electron traps Electronics embedded memory Exact sciences and technology gate-induced drain leakage (GIDL) GIDL program Integrated circuits Integrated circuits by function (including memories and processors) Leakage current Logic gates Nitrides Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sensors soft erasing SONOS SONOS devices Stress measurement Transistors unified random access memory (URAM) |
| title | Improvement of the Sensing Window on a Capacitorless 1T-DRAM of a FinFET-Based Unified RAM |
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