A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS: Special Issue on the 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)

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Veröffentlicht in:IEEE journal of solid-state circuits 2009, Vol.44 (7), p.1927-1941
Hauptverfasser: RODONI, Lucio, VON BÜREN, George, HUBER, Alex, SCHMATZ, Martin, JÄCKEL, Heinz
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container_end_page 1941
container_issue 7
container_start_page 1927
container_title IEEE journal of solid-state circuits
container_volume 44
creator RODONI, Lucio
VON BÜREN, George
HUBER, Alex
SCHMATZ, Martin
JÄCKEL, Heinz
description
format Article
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ispartof IEEE journal of solid-state circuits, 2009, Vol.44 (7), p.1927-1941
issn 0018-9200
1558-173X
language eng
recordid cdi_pascalfrancis_primary_21975249
source IEEE/IET Electronic Library (IEL)
subjects Applied sciences
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
title A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS: Special Issue on the 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)
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