Interests and Limitations of Technology Scaling for Subthreshold Logic

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2009-10, Vol.17 (10), p.1508-1519
Hauptverfasser:	Bol, D., Ambroise, R., Flandre, D., Legat, J.-D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Channels Circuits CMOS digital integrated circuits CMOS technology Degradation Delay Design. Technologies. Operation analysis. Testing Dynamics Electric potential Electronics Energy consumption Energy efficiency Exact sciences and technology Integrated circuits Logic Logic circuits Logic devices MOSFET circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices subthreshold logic technology scaling Throughput ultralow power (ULP) variability Very large scale integration Voltage
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