Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory
In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfigurat...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on magnetics 2009-02, Vol.45 (2), p.776-780 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 780 |
|---|---|
| container_issue | 2 |
| container_start_page | 776 |
| container_title | IEEE transactions on magnetics |
| container_volume | 45 |
| creator | Weisheng Zhao Belhaire, E. Chappert, C. Mazoyer, P. |
| description | In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model. |
| doi_str_mv | 10.1109/TMAG.2008.2006872 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_pascalfrancis_primary_21471889</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4782120</ieee_id><sourcerecordid>2292008311</sourcerecordid><originalsourceid>FETCH-LOGICAL-c385t-adbfe53bee31d419d845962123fadec91020eadfe3cbb89e7daa3525ab97c1173</originalsourceid><addsrcrecordid>eNp9kU2P0zAQhiMEEmXhByAuFhJwyuKPOLGPpYIFaauuSjlbE2dSvIrjYidChT-PS6s9cOAyo9E8845m3qJ4yeg1Y1S_362XN9ecUnUKtWr4o2LBdMXKXOnHxYJSpkpd1dXT4llK97msJKOL4vdd-ImRwNiRZUQgm8PkvPsFkwsj6UMk23ksd84j2aINY-_2czw3vx7ThJ5sRnIXwz6C99AOSFbf3YF8gIQdydAa9iNOzpJt3hA8WVqLKZE1-hCPz4snPQwJX1zyVfHt08fd6nN5u7n5slrellYoOZXQtT1K0SIK1lVMd6qSuuaMix46tJpRThG6HoVtW6Wx6QCE5BJa3VjGGnFVvDvrHmL4MWOajHfJ4jDAiGFORtVaSaE4z-Tb_5KiqmspKM3g63_A-zDHMV9hlKw151LpDLEzZGNIKWJvDtF5iEfDqDm5Zk6umZNr5uJannlzEYZkYegjjNalh0HOqoapv9qvzpxDxId21aj8Fyr-AOPsoPY</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>856922589</pqid></control><display><type>article</type><title>Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory</title><source>IEEE Electronic Library (IEL)</source><creator>Weisheng Zhao ; Belhaire, E. ; Chappert, C. ; Mazoyer, P.</creator><creatorcontrib>Weisheng Zhao ; Belhaire, E. ; Chappert, C. ; Mazoyer, P.</creatorcontrib><description>In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model.</description><identifier>ISSN: 0018-9464</identifier><identifier>EISSN: 1941-0069</identifier><identifier>DOI: 10.1109/TMAG.2008.2006872</identifier><identifier>CODEN: IEMGAQ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Application specific integrated circuits ; Chips (memory devices) ; Circuit simulation ; Cross-disciplinary physics: materials science; rheology ; Delay ; Exact sciences and technology ; Field programmable gate arrays ; Flip-flop ; FPGA ; low power and low die area ; LUT ; Magnetic tunneling ; Magnetism ; Magnetoresistive random access memory ; Materials science ; Mathematical models ; MRAM ; nonvolatile ; Nonvolatile memory ; Other topics in materials science ; Physics ; Random access memory ; Reconfiguration ; Run time (computers) ; run-time reconfiguration ; Runtime ; SOPC ; Switching circuits ; Table lookup ; Tunnel junctions</subject><ispartof>IEEE transactions on magnetics, 2009-02, Vol.45 (2), p.776-780</ispartof><rights>2009 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c385t-adbfe53bee31d419d845962123fadec91020eadfe3cbb89e7daa3525ab97c1173</citedby><cites>FETCH-LOGICAL-c385t-adbfe53bee31d419d845962123fadec91020eadfe3cbb89e7daa3525ab97c1173</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4782120$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4782120$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=21471889$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Weisheng Zhao</creatorcontrib><creatorcontrib>Belhaire, E.</creatorcontrib><creatorcontrib>Chappert, C.</creatorcontrib><creatorcontrib>Mazoyer, P.</creatorcontrib><title>Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory</title><title>IEEE transactions on magnetics</title><addtitle>TMAG</addtitle><description>In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model.</description><subject>Application specific integrated circuits</subject><subject>Chips (memory devices)</subject><subject>Circuit simulation</subject><subject>Cross-disciplinary physics: materials science; rheology</subject><subject>Delay</subject><subject>Exact sciences and technology</subject><subject>Field programmable gate arrays</subject><subject>Flip-flop</subject><subject>FPGA</subject><subject>low power and low die area</subject><subject>LUT</subject><subject>Magnetic tunneling</subject><subject>Magnetism</subject><subject>Magnetoresistive random access memory</subject><subject>Materials science</subject><subject>Mathematical models</subject><subject>MRAM</subject><subject>nonvolatile</subject><subject>Nonvolatile memory</subject><subject>Other topics in materials science</subject><subject>Physics</subject><subject>Random access memory</subject><subject>Reconfiguration</subject><subject>Run time (computers)</subject><subject>run-time reconfiguration</subject><subject>Runtime</subject><subject>SOPC</subject><subject>Switching circuits</subject><subject>Table lookup</subject><subject>Tunnel junctions</subject><issn>0018-9464</issn><issn>1941-0069</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kU2P0zAQhiMEEmXhByAuFhJwyuKPOLGPpYIFaauuSjlbE2dSvIrjYidChT-PS6s9cOAyo9E8845m3qJ4yeg1Y1S_362XN9ecUnUKtWr4o2LBdMXKXOnHxYJSpkpd1dXT4llK97msJKOL4vdd-ImRwNiRZUQgm8PkvPsFkwsj6UMk23ksd84j2aINY-_2czw3vx7ThJ5sRnIXwz6C99AOSFbf3YF8gIQdydAa9iNOzpJt3hA8WVqLKZE1-hCPz4snPQwJX1zyVfHt08fd6nN5u7n5slrellYoOZXQtT1K0SIK1lVMd6qSuuaMix46tJpRThG6HoVtW6Wx6QCE5BJa3VjGGnFVvDvrHmL4MWOajHfJ4jDAiGFORtVaSaE4z-Tb_5KiqmspKM3g63_A-zDHMV9hlKw151LpDLEzZGNIKWJvDtF5iEfDqDm5Zk6umZNr5uJannlzEYZkYegjjNalh0HOqoapv9qvzpxDxId21aj8Fyr-AOPsoPY</recordid><startdate>20090201</startdate><enddate>20090201</enddate><creator>Weisheng Zhao</creator><creator>Belhaire, E.</creator><creator>Chappert, C.</creator><creator>Mazoyer, P.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8BQ</scope><scope>8FD</scope><scope>JG9</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20090201</creationdate><title>Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory</title><author>Weisheng Zhao ; Belhaire, E. ; Chappert, C. ; Mazoyer, P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c385t-adbfe53bee31d419d845962123fadec91020eadfe3cbb89e7daa3525ab97c1173</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Application specific integrated circuits</topic><topic>Chips (memory devices)</topic><topic>Circuit simulation</topic><topic>Cross-disciplinary physics: materials science; rheology</topic><topic>Delay</topic><topic>Exact sciences and technology</topic><topic>Field programmable gate arrays</topic><topic>Flip-flop</topic><topic>FPGA</topic><topic>low power and low die area</topic><topic>LUT</topic><topic>Magnetic tunneling</topic><topic>Magnetism</topic><topic>Magnetoresistive random access memory</topic><topic>Materials science</topic><topic>Mathematical models</topic><topic>MRAM</topic><topic>nonvolatile</topic><topic>Nonvolatile memory</topic><topic>Other topics in materials science</topic><topic>Physics</topic><topic>Random access memory</topic><topic>Reconfiguration</topic><topic>Run time (computers)</topic><topic>run-time reconfiguration</topic><topic>Runtime</topic><topic>SOPC</topic><topic>Switching circuits</topic><topic>Table lookup</topic><topic>Tunnel junctions</topic><toplevel>online_resources</toplevel><creatorcontrib>Weisheng Zhao</creatorcontrib><creatorcontrib>Belhaire, E.</creatorcontrib><creatorcontrib>Chappert, C.</creatorcontrib><creatorcontrib>Mazoyer, P.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on magnetics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Weisheng Zhao</au><au>Belhaire, E.</au><au>Chappert, C.</au><au>Mazoyer, P.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory</atitle><jtitle>IEEE transactions on magnetics</jtitle><stitle>TMAG</stitle><date>2009-02-01</date><risdate>2009</risdate><volume>45</volume><issue>2</issue><spage>776</spage><epage>780</epage><pages>776-780</pages><issn>0018-9464</issn><eissn>1941-0069</eissn><coden>IEMGAQ</coden><abstract>In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TMAG.2008.2006872</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9464 |
| ispartof | IEEE transactions on magnetics, 2009-02, Vol.45 (2), p.776-780 |
| issn | 0018-9464 1941-0069 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_21471889 |
| source | IEEE Electronic Library (IEL) |
| subjects | Application specific integrated circuits Chips (memory devices) Circuit simulation Cross-disciplinary physics: materials science rheology Delay Exact sciences and technology Field programmable gate arrays Flip-flop FPGA low power and low die area LUT Magnetic tunneling Magnetism Magnetoresistive random access memory Materials science Mathematical models MRAM nonvolatile Nonvolatile memory Other topics in materials science Physics Random access memory Reconfiguration Run time (computers) run-time reconfiguration Runtime SOPC Switching circuits Table lookup Tunnel junctions |
| title | Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T17%3A56%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Power%20and%20Area%20Optimization%20for%20Run-Time%20Reconfiguration%20System%20On%20Programmable%20Chip%20Based%20on%20Magnetic%20Random%20Access%20Memory&rft.jtitle=IEEE%20transactions%20on%20magnetics&rft.au=Weisheng%20Zhao&rft.date=2009-02-01&rft.volume=45&rft.issue=2&rft.spage=776&rft.epage=780&rft.pages=776-780&rft.issn=0018-9464&rft.eissn=1941-0069&rft.coden=IEMGAQ&rft_id=info:doi/10.1109/TMAG.2008.2006872&rft_dat=%3Cproquest_RIE%3E2292008311%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=856922589&rft_id=info:pmid/&rft_ieee_id=4782120&rfr_iscdi=true |