Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel

To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo decoder is proposed. In this paper, we systematically analyze the timing charts of both the Viterbi algorithm and the MAP...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2008-10, Vol.16 (10), p.1358-1371
Hauptverfasser:	LI, Fan-Min, LIN, Cheng-Hung, WU, An-Yeu
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithm design and analysis Algorithms Applied sciences Charts Circuit properties Code standards Construction Convolutional code Convolutional codes Decoders Decoding Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology forward-error-correction code Integrated circuits Integrated circuits by function (including memories and processors) Kernel Kernels log-MAP maximum a-posteriori probability Prototypes reconfigurable FEC architecture Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Throughput Time measurements Timing turbo code Turbo codes Viterbi algorithm
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!