Operational Voltage Reduction of Flash Memory Using High- \kappa Composite Tunnel Barriers
We explore the performance of symmetric (low-k/high-k/low-k) and asymmetric (low-k/high-k) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-k materials, were performed under these criteria to mini...
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| Veröffentlicht in: | IEEE electron device letters 2008-03, Vol.29 (3), p.252-254 |
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| container_title | IEEE electron device letters |
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| creator | Verma, S. Pop, E. Kapur, P. Parat, K. Saraswat, K.C. |
| description | We explore the performance of symmetric (low-k/high-k/low-k) and asymmetric (low-k/high-k) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-k materials, were performed under these criteria to minimize the programming voltage V prog . Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V prog and choosing the high-k materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V prog of ~ 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% -40% lower than the prevalent voltages. |
| doi_str_mv | 10.1109/LED.2007.915376 |
| format | Article |
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Simulations, including five different high-k materials, were performed under these criteria to minimize the programming voltage V prog . Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V prog and choosing the high-k materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V prog of ~ 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% -40% lower than the prevalent voltages.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2007.915376</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Composite materials ; Design optimization ; Design. Technologies. Operation analysis. Testing ; Dielectric materials ; Electronics ; Electrons ; Exact sciences and technology ; Flash memory ; Flash operating constraints ; high- kappa dielectrics ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Materials science and technology ; Memory management ; Nonvolatile memory ; program disturb ; read disturb ; retention ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Simulations, including five different high-k materials, were performed under these criteria to minimize the programming voltage V prog . Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V prog and choosing the high-k materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V prog of ~ 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% -40% lower than the prevalent voltages.</description><subject>Applied sciences</subject><subject>Composite materials</subject><subject>Design optimization</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dielectric materials</subject><subject>Electronics</subject><subject>Electrons</subject><subject>Exact sciences and technology</subject><subject>Flash memory</subject><subject>Flash operating constraints</subject><subject>high- kappa dielectrics</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Materials science and technology</subject><subject>Memory management</subject><subject>Nonvolatile memory</subject><subject>program disturb</subject><subject>read disturb</subject><subject>retention</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>tunnel barrier engineering</subject><subject>Voltage</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMFLwzAUh4MoOKdnD15y8dgtaZImO-rcnDAZyOZBhJK0L1u0a0rSHfbf21HZ6cHvfb_H40PonpIRpWQyXs5eRikhcjShgsnsAg2oECohImOXaEAkpwmjJLtGNzH-EEI5l3yAvlYNBN06X-sKf_qq1VvAH1AeilOGvcXzSscdfoe9D0e8ia7e4oXb7hL8_aubRuOp3zc-uhbw-lDXUOFnHYKDEG_RldVVhLv_OUSb-Ww9XSTL1evb9GmZFEzINhFGTohV1gjKCWOFMZJBmTIlACxVmbCmy8vSSNP9r3TKCHSoVIYKrkrDhmjc3y2CjzGAzZvg9jocc0ryk5q8U5Of1OS9mq7x2DcaHQtd2aDrwsVzLe3kCJamHffQcw4AzmvOhchUxv4AqPNsVg</recordid><startdate>20080301</startdate><enddate>20080301</enddate><creator>Verma, S.</creator><creator>Pop, E.</creator><creator>Kapur, P.</creator><creator>Parat, K.</creator><creator>Saraswat, K.C.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20080301</creationdate><title>Operational Voltage Reduction of Flash Memory Using High- \kappa Composite Tunnel Barriers</title><author>Verma, S. ; Pop, E. ; Kapur, P. ; Parat, K. ; Saraswat, K.C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c357t-5b790f8fb514033cbb73ed2385eef1865fb403ddb7b3108a230e51478b1548db3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Applied sciences</topic><topic>Composite materials</topic><topic>Design optimization</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Dielectric materials</topic><topic>Electronics</topic><topic>Electrons</topic><topic>Exact sciences and technology</topic><topic>Flash memory</topic><topic>Flash operating constraints</topic><topic>high- kappa dielectrics</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Materials science and technology</topic><topic>Memory management</topic><topic>Nonvolatile memory</topic><topic>program disturb</topic><topic>read disturb</topic><topic>retention</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>tunnel barrier engineering</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Verma, S.</creatorcontrib><creatorcontrib>Pop, E.</creatorcontrib><creatorcontrib>Kapur, P.</creatorcontrib><creatorcontrib>Parat, K.</creatorcontrib><creatorcontrib>Saraswat, K.C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Verma, S.</au><au>Pop, E.</au><au>Kapur, P.</au><au>Parat, K.</au><au>Saraswat, K.C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Operational Voltage Reduction of Flash Memory Using High- \kappa Composite Tunnel Barriers</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2008-03-01</date><risdate>2008</risdate><volume>29</volume><issue>3</issue><spage>252</spage><epage>254</epage><pages>252-254</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>We explore the performance of symmetric (low-k/high-k/low-k) and asymmetric (low-k/high-k) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-k materials, were performed under these criteria to minimize the programming voltage V prog . Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V prog and choosing the high-k materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V prog of ~ 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% -40% lower than the prevalent voltages.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2007.915376</doi><tpages>3</tpages></addata></record> |
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| subjects | Applied sciences Composite materials Design optimization Design. Technologies. Operation analysis. Testing Dielectric materials Electronics Electrons Exact sciences and technology Flash memory Flash operating constraints high- kappa dielectrics Integrated circuits Integrated circuits by function (including memories and processors) Materials science and technology Memory management Nonvolatile memory program disturb read disturb retention Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices tunnel barrier engineering Voltage |
| title | Operational Voltage Reduction of Flash Memory Using High- \kappa Composite Tunnel Barriers |
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